The benchmarks were achieved during scaling experiments on 5nm test chips and a full reticle-sized 7nm production design on Azure. In these deployments, Calibre scaled out to more than 4,000 CPUs – an industry record for an EDA tool scaling a single job on Azure. Mentor and Azure plan additional experiments to demonstrate further scaling and establish recommended chip design sizes to help mutual customers achieve their target runtimes in cloud deployments.
“Mentor is pleased to have partnered with Microsoft Azure to define a new benchmark with Calibre for scaling for Semiconductor Design Workloads,” said Michael Buehler-Garcia, vice president of product management, Calibre Design Solutions for Mentor. “As IC companies increasingly look to leverage cloud capacity for faster turnaround times on advanced process node designs, they can be confident that their designs will optimally scale in Microsoft Azure’s robust, secure cloud environment.”
“Calibre has set a new benchmark for EDA tool performance, scalability and efficient memory use – all metrics of increasingly critical importance as new semiconductor process nodes introduce unparalleled complexity and encourage ever-larger CPU runs,” said Mujtaba Hamid, head of Product Management, Silicon, Electronics and Gaming, Azure Engineering, Microsoft Corp. “Calibre supports the rapidly evolving requirements of our semiconductor customers, while demonstrating the outstanding security and performance that Microsoft Azure cloud offers to the demanding EDA market.”
Used throughout the global semiconductor ecosystem as the signoff physical verification solution of choice, Mentor’s Calibre platform continues to set the pace for verification accuracy, reliability and performance. IC designers can use Calibre in any design flow, and while running on either traditional in-house compute configurations or in public cloud environments such as Microsoft Azure.
At DAC 2019 in Las Vegas, Mentor and Microsoft Azure will host a luncheon session on Tuesday, June 4 at 12:00pm, where attendees can learn more about the latest strategies and technologies available for cloud-based IC design. To register please visit: https://bit.ly/2V5XhdY.