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Mentor and AMD verify massive Radeon Instinct Vega20 IC design on AMD EPYC in ~10 hours with ecosystem partners Microsoft Azure and TSMC

Published May 30, 2019

AMD engineers executed a physical verification pass of the Radeon Instinct™ Vega20 — its largest 7nm chip design — in ~10 hours using the TSMC-certified Calibre™ nmDRC software platform from Mentor, a Siemens business, running on the Microsoft Azure cloud platform using HB-series virtual machines, powered by AMD EPYC™ processors.

Using TSMC 7nm Calibre design kits running in Azure, AMD successfully completed two verification passes in ~19 hours – a dramatic reduction in total physical verification turnaround time, despite the massive 13.2B transistors on the AMD design. In addition, AMD scaled Calibre nmDRC out to 4,140 cores across 69 HB virtual machines, enabling its engineers to balance tight deadlines against demanding resource requirements and other costs.

Mentor paved the way for this milestone on Azure with new scaling and memory consumption enhancements designed to help its Calibre software customers reduce memory requirements and associated costs. The enhancements are also engineered to help drastically streamline physical verification run times when using either traditional, private on-premise “fog”, or cloud-based configurations. Mentor joined with TSMC and AMD to implement these enhancements and verify the optimized results using the latest version of Calibre nmDRC.

“AMD demands speed and quality of execution in our cutting-edge semiconductor design work, so achieving two verification passes in one day in the cloud is critical to getting future designs to market,” said Daniel Bounds, senior director, AMD Datacenter Products. “AMD is pleased to see that Mentor’s Calibre nmDRC scales on cloud-based AMD EPYC-powered servers not just in traditional use models, but also on the Azure public cloud.”

Recent enhancements to Calibre have enabled multiple customers to reduce memory requirements by as much as 50 percent in both cloud and traditional configurations for full chip verification runs on their latest 7nm designs. Memory requirements are a key cost driver for both public cloud and fog computing, and Calibre has long led the industry in efficient memory utilization.

“Mentor continues to enhance our software solutions to help customers speed time-to-market, regardless of where they elect to run their physical verification,” said Joe Sawicki, executive vice president, Mentor IC EDA. “We are pleased to expand our collaboration with TSMC so our mutual customers running on third-party clouds can fully leverage both TSMC process technology and Mentor’s software platforms, providing them with additional options to more quickly deliver ICs manufactured on TSMC’s new processes.”

TSMC recently certified Mentor’s Calibre tool to run on TSMC’s 5nm FinFET process technology in cloud flows hosted by Microsoft Azure and other leading cloud services providers. Mentor has also been named a member of the TSMC OIP Cloud Alliance, broadening TSMC’s OIP ecosystem with new cloud-ready design solutions, and helping customers unleash innovations with TSMC process technology.

“With this latest achievement, Mentor has again demonstrated its value to the TSMC OIP ecosystem,” said Suk Lee, TSMC senior director, Design Infrastructure Management Division. “We’re pleased with this result of collaborative efforts combining TSMC’s process technology and design enablement with Mentor’s design platform and Microsoft Azure’s cloud service in achieving this notable milestone.”

At DAC 2019 Las Vegas, Mentor, AMD, Microsoft Azure and TSMC will host a luncheon session from noon to 1:30 pm on Tuesday, June 4 at the Westgate Hotel, Westgate Ballroom D-E, where attendees can learn more about the latest strategies and technologies available for cloud-based IC design. To register please visit: https://bit.ly/2V5XhdY.

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