industry news
Subscribe Now

Enhanced Serial Peripheral Interface (eSPI) Master/Slave Controller

DCD-SEMI, a leading IP Core provider and SoC design house from Poland has mastered unique DeSPI IP Core. It is a fully configurable eSPI master/slave device supporting all features described in the Enhanced Serial Peripheral Interface Base Specification rev. 1.0. The DESPI master is to be used by the microcontroller to communicate with eSPI peripheral devices. The DESPI slave is to be used as an eSPI peripheral device, e.g., an Embedded Controller attached to the Intel CPU system.

Bytom, Poland June the 28th, 2022. The eSPI bus is an LPC bus improvement. The serial clock line (_sck) synchronizes shifting and sampling of the information on the IO lines. – It is a technology-independent design that can be implemented in a variety of process technologies – explains Jacek Hanke, DCD-SEMI CEO. 

The DESPI is flexible enough to interface directly with numerous peripherals. The system may be configured either as master or as slave, and depending on the core configuration, the _in or _out lines will be utilized. Its serial clock can run up to 66MHz – adds Hanke.

The DESPI is also capable of simple, dual, and quad SPI transfers. The DESPI is fully customizable, which means it is delivered in the exact configuration with the target design requirements. Additionally, the DESPI module is equipped with receiver and transmitter FIFOs, capable of storing up to 4096+16 bytes (Header and maximal data payload) in separate buffers for every eSPI channel. (Peripheral Channel Posted and Non-Posted, Virtual Wire Channel, Out of Band Channel, Flash Access Channel). 

Additionally, customizable Peripheral Channel Memory and IO port, Virtual Wire lines and event lines are also supported. An interesting and unique feature is the Alert mechanism, used by the eSPI Slave to request service from the eSPI master.

The controller is capable to operate in several eSPI configurations: 

  • Single Master- Single Slave, 
  • Single Master – Multiple Slaves. 

The DCD SPI cores, are part of our growing peripheral family that also includes protocols such as I3C and IR. The DCD SPI cores have been successfully implemented in Embedded Microprocessor Boards, Consumer and Professional Audio/Video, Home and Automotive Radio, Low-power Mobile Applications, Communication Systems, and Digital Multimeters.

More information: 


DCD-SEMI has two decades of IP market experience. The company was founded in 1999 in Bytom, Poland and has mastered more than 70 different architectures, among them the World’s Fastest 8051 CPU, Royalty-Free and Fully Scalable 32-bit CPU and 100% cryptographic system. Automotive IP Cores designed by DCD-SEMI are offered as CAN ALL package – a tailored made IP Core which have been successfully implemented by dozens of automotive companies such as VW, Toyota and now GuardKnox. More information can be found at:, and

Leave a Reply

featured blogs
Aug 12, 2022
Relive Design Automation Conference (DAC) 2022 with intern Samir Banerjee, including the latest on cloud EDA tools, climate action, and diversity in engineering. The post Reflecting on the 59th Design Automation Conference (DAC) appeared first on From Silicon To Software....
Aug 11, 2022
Speed increase requirements keep on flowing by in all the domains surrounding us . The s ame applies to memory storage too . Earlier mobile devices used eMMC based flash storage, which was a significantly slower technology. With increased SoC processing speed, pairing it with...
Jul 27, 2022
It's easy to envisage a not-so-distant future when sophisticated brain-computer interfaces become available for general-purpose infotainment use....

featured video

Learn How Xcelium Apps Help You Achieve Verification Closure Early for IP/SoC Designs

Sponsored by Cadence Design Systems

Cadence Xcelium Logic Simulator provides the best engine performance for SystemVerilog, VHDL, SystemC®, e, UVM, mixed-signal, low power, and X-propagation. It leverages a set of domain-specific apps, including mixed-signal, machine learning, functional safety, and more, that enable users to achieve verification closure early for IP and SoC designs. Learn how these domain-specific apps can help you achieve verification closure early for IP and SoC designs.

Click here to learn more

featured chalk talk

Enabling the Flow of Data in the World of IoT

Sponsored by Mouser Electronics and YAGEO Group

At the heart of our growing IoT ecosystem are high performance semiconductors, but integrated circuits alone cannot make a successful IoT system. In this episode of Chalk Talk, Amelia Dalton chats with Peter Blais from KEMET and Ryan Wenzelman from Pulse about how passive components are crucial to the development of successful IoT frameworks. They take a closer look at RF, wired and power distribution aspects of IoT system development and investigate how YAGEO Group is advancing innovation in the world of IoT with a wide selection of passive components.

Click here for more information about Pulse Electronics World of IoT