industry news
Subscribe Now

DVCon Europe Announces two extra Keynotes and full Technical Program

Virtual event incorporates Virtual Experience Rooms for easy networking

Munich, Germany – 6th October, 2020 – The Design and Verification Conference & Exhibition Europe (DVCon Europe), sponsored by Accellera Systems Initiative, has announced two new keynote speakers and a full technical program.  The 2020 conference has been transformed into a virtual event, incorporating a Virtual Reality 3D world for easy networking, and will be held from October 27th to 28th 2020. Registration is now open and a discount applies until October 22nd. In addition, 30 free academic passes will be offered to university students across Europe.

Technical Program and Virtual Experience Rooms

The conference covers, in addition to the four keynote speakers, a strong technical program with 24 papers, 11 posters, 13 tutorials and two panels. The conference highlights are available here: https://dvcon-europe.org/conference-highlights .  In parallel to the main program, which uses a regular web-based conferencing system, DVCon Europe aims to introduce a true virtual 3D experience by hosting various Virtual Experience Rooms.  This virtual venue will be used for the poster sessions and to enable interaction, collaboration and networking during coffee breaks and to encourage discussions amongst participants outside of the presentation sessions.

Keynotes from Industry Luminaries

The two new keynotes are from Dr Mike Mayberry, Chief Technology Officer at Intel Corporation, who will present: ‘The Future of Compute: Verification in the Era of Heterogeneous Design’, and Moshe Zalcberg, Chief Executive Officer of Veriest Solutions, whose presentation is entitled:  ‘I like being surrounded by good ideas: any good ideas we can borrow from the software world?’  These join previously announced keynotes from Victoria (Vicki) Mitchell, VP Systems Engineering at Arm, and Dr. Matthias Traub, Head of Architecture and Technologies at Volkswagen.  Vicki Mitchell’s keynote will be entitled ‘The Benefits of Hardware DevOps’, and Dr. Matthias Traub will present ‘Challenges of a Sustainable Innovative Automotive Computing Architecture’.

Joachim Geishauser, General Chair of DVCon Europe, explained that the keynotes match the aim of the conference; to bring hardware and software engineers together. “The keynote speakers will be sharing their insights into the adoption of new methodologies and verification approaches and will discuss how the formerly separated disciplines of hardware and software are being adapted to a new ‘system thinking’.”

The detailed keynote abstracts and biographies of the keynote speakers are available here:  https://dvcon-europe.org/keynote-speakers

ABOUT DVCON EUROPE

The Design and Verification Conference & Exhibition in Europe (DVCon Europe) is the leading European event covering the application of languages, tools and intellectual property for the design and verification of electronic systems and integrated circuits. Sponsored by Accellera Systems Initiative, and one of several DVCon events around the globe, DVCon Europe brings chip architects, design & verification engineers, and IP integrators the latest methodologies, techniques, applications and demonstrations for the practical use of EDA solutions for electronic design. For more details, visit www.dvcon-europe.org. Follow #dvconeurope on Twitter.

ABOUT ACCELLERA SYSTEMS INITIATIVE

Accellera Systems Initiative (Accellera) is an independent, not-for profit organization, dedicated to create, support, promote and advance system-level design, modeling and verification standards for use by the worldwide electronics industry. The organization accelerates standards development and, as part of its ongoing partnership with the IEEE, its standards are contributed to the IEEE Standards Association for formal standardization and ongoing change control. For more information, please visit accellera.org. For membership information, please email membership@accellera.org. Follow @accellera on Twitter or to comment, please use #accellera.

Leave a Reply

featured blogs
Jan 15, 2021
I recently saw (what appears at first glance to be) a simple puzzle involving triangles. But is finding the solution going to be trickier than I think?...
Jan 15, 2021
It's Martin Luther King Day on Monday. Cadence is off. Breakfast Bytes will not appear. And, as is traditional, I go completely off-topic the day before a break. In the past, a lot of novelty in... [[ Click on the title to access the full blog on the Cadence Community s...
Jan 14, 2021
Learn how electronic design automation (EDA) tools & silicon-proven IP enable today's most influential smart tech, including ADAS, 5G, IoT, and Cloud services. The post 5 Key Innovations that Are Making Everything Smarter appeared first on From Silicon To Software....
Jan 13, 2021
Testing is the final step of any manufacturing process, and arguably the most important, and yet it can often be overlooked.  Releasing a poorly tested product onto the market has destroyed more than one reputation for quality, and this is even more important in an age when ...

featured paper

Common Design Pitfalls When Designing With Hall 2D Sensors And How To Avoid Them

Sponsored by Texas Instruments

This article discusses three widespread application issues in industrial and automotive end equipment – rotary encoding, in-plane magnetic sensing, and safety-critical – that can be solved more efficiently using devices with new features and higher performance. We will discuss in which end products these applications can be found and also provide a comparison with our traditional digital Hall-effect sensors showing how the new releases complement our existing portfolio.

Click here to download the whitepaper

Featured Chalk Talk

TensorFlow to RTL with High-Level Synthesis

Sponsored by Cadence Design Systems

Bridging the gap from the AI and data science world to the RTL and hardware design world can be challenging. High-level synthesis (HLS) can provide a mechanism to get from AI frameworks like TensorFlow into synthesizable RTL, enabling the development of high-performance inference architectures. In this episode of Chalk Talk, Amelia Dalton chats with Dave Apte of Cadence Design Systems about doing AI design with HLS.

More information