Drive for richer graphics, higher data throughput and wider range of multimedia forces engineers to enable more sophisticated features in embedded applications. But the higher data throughputs require extra demands on the often-limited MCU on-chip memory. That’s why DCD-SEMI mastered DOSPI – octa SPI, to enhance the line of dual and quad SPI IP Cores.
Bytom, Poland, September the 21st, 2021. External parallel memories have been widely used so far to provide higher data throughput and to extend the MCU on-chip memory, solving the memory size and the performance limitation. However, this compromises the pin count and implies a need of more complex designs and higher cost.
To meet these requirements, DCD-SEMI introduced the DOSPI IP Core, which supports all 8-, 16- and 32-bit CPUs. – The Octa SPI interface enables the connection of the external compact-footprint – explain Jacek Hanke, DCD’s CEO – Thanks to its low-pin count, the octa SPI interface allows easier PCB designs and lower costs.
We cannot forget that thanks to its high throughput, the DOSPI allows in place code execution (XIP) and data storage. The external memory can be accessed as if it was an internal memory allowing the system masters (such as DMA or SDMMC) to access autonomously, even in low-power mode when the CPU is stopped, which seems to answer the mobile world needs.
DOSPI bridge to APB, AHB, AXI bus offers the fastest operations available for any serial SPI memory. It is flexible enough to interface directly with numerous standard product peripherals from several manufacturers. The DOSPI is a fully configurable SPI master/slave device, which allows to configure polarity and phase of serial clock signal SCK. It enables the microcontroller to communicate with fast serial SPI memories and serial peripheral devices. In the Single SPI mode, data is simultaneously transmitted and received, while in DUAL, QUAD and OCTAL SPI modes, data is shifted in or out respectively on two, four and eight data lines at once. – Last but not least we need to add that the transfer speed can be doubled by using the DDR protocol (Double Data Rate) – says Jacek Hanke, DCD’s CEO. This feature allows the DOSPI to transfer/receive data on both falling and rising edges of SCK. The DDR together with OCTAL SPI transfer allow 8 bits of data to be sent/received within a single SCK clock cycle. This makes the DOSPI perfect for systems, where performance is essential.
DCD’s IP Core is a technology independent design that can be implemented in variety of process technologies. The DOSPI system is flexible enough to interface directly with numerous standard product peripherals from several manufacturers. The system can be configured as a master or slave device. Data rates as high as CLK/2, when other vendors’ solutions offer just CLK/8. Error‐detection logic is included, to support interprocessor communications. A write‐collision detector indicates when an attempt is made to write data to the serial shift register, while the transfer is in progress. A multiple-master mode‐fault detector disables DOSPI output drivers automatically, if more than one SPI device simultaneously attempts to become a bus master. The DOSPI supports two DMA modes: single transfer and multi‐transfer.
More information and datasheets can be found here: