industry news
Subscribe Now

Credo Announces First Offering of 800G HiWire Active Electrical Cables for Next Generation Decentralized Data Centers and AI Servers

800G HiWire AECs decrease cabling volume by up to 75% less over traditional direct-attached copper cables while improving reliability and consuming 50% less power than optical cabling

San Jose, Calif., October 28, 2021 – Credo, a global leader in high-performance, low-power connectivity solutions for 100G, 400G, and 800G port-enabled networks, today announced the new 800G HiWire™ LP CLOS Active Electrical Cable (AEC) designed for distributed, disaggregated chassis (DDCs) used in hyperscale infrastructure.  This 8 x 112G per lane copper cable interconnect is the first member of Credo’s 800G AEC family.

At 400G and higher, AECs offer greater signal integrity and break through the physical weight, bend radius, and range limits of passive copper Direct Attached Cables (DACs). AECs also lower the power and economic barriers of Active Optical Cables (AOCs). The hot-swappable, front-plane cables enable a data center infrastructure shift from homogenous chassis designs with tightly coupled operating systems to DDC implementations.  DDC architectures deliver the freedom to mix-and-match servers, switches, and operating systems to suit specific performance, power, and price points.

“Credo sees 800G as the point where passive DACs hit the wall – they are far too thick and rigid for many customer applications and impose a high cost and engineering burden on switch manufacturers,” said Don Barnetson, Vice President of Product at Credo. “Credo’s new 800G LP CLOS AECs route like Cat6 cables and offer up to 100 times better reliability and half the power of optical cabling solutions. The future of connectivity is clearly purple.”

At just 32AWG, 800G AECs are about as thick as standard Cat6e cabling. This narrower gauge reduces cabling volume by up to 75% versus passive copper DACs. LP CLOS AECs are available in lengths up to 2.5m. Credo’s new AECs consume half as much power as optical cabling solutions and feature superior reliability with up to 100 million hours of Mean Time Between Failure (MTBF).

The LP CLOS AEC 800 PAM4 cables come in QSFP-DD800 (Quad Small Form Factor Pluggable Multi-Source Agreement Group) and OSFP (Octal Small Form Factor Pluggable) types. Integrated Credo retimers enable the cable to achieve high performance without needing additional external components, simplifying the design and lowering system cost and power.

As with all Credo AECs, the new 800G AECs are easily identified by their distinctive HiWire purple color sheath. Credo is sampling the LP CLOS AEC 800 now with general availability expected in early 2022.

For more information about HiWire 800G AECs, visit https://www.credosemi.com/credo-hiwire-lp-clos-aec-active-electrical-cable.

About Credo
Credo is a leading provider of high-performance serial connectivity solutions for the hyperscale datacenter, 5G carrier, enterprise networking, artificial intelligence, and high-performance computing markets. Credo’s solutions deliver the bandwidth, scalability, and end-to-end signal integrity for next-generation platforms requiring 25G, 50G, and 100G signal lane-rate connectivity for 100G, 200G, 400G, and 800G port enabled networks.

For more information, please visit https://www.credosemi.com. Follow Credo on LinkedIn and Twitter.

Leave a Reply

featured blogs
Apr 25, 2024
Structures in Allegro X layout editors let you create reusable building blocks for your PCBs, saving you time and ensuring consistency. What are Structures? Structures are pre-defined groups of design objects, such as vias, connecting lines (clines), and shapes. You can combi...
Apr 25, 2024
See how the UCIe protocol creates multi-die chips by connecting chiplets from different vendors and nodes, and learn about the role of IP and specifications.The post Want to Mix and Match Dies in a Single Package? UCIe Can Get You There appeared first on Chip Design....
Apr 18, 2024
Are you ready for a revolution in robotic technology (as opposed to a robotic revolution, of course)?...

featured video

How MediaTek Optimizes SI Design with Cadence Optimality Explorer and Clarity 3D Solver

Sponsored by Cadence Design Systems

In the era of 5G/6G communication, signal integrity (SI) design considerations are important in high-speed interface design. MediaTek’s design process usually relies on human intuition, but with Cadence’s Optimality Intelligent System Explorer and Clarity 3D Solver, they’ve increased design productivity by 75X. The Optimality Explorer’s AI technology not only improves productivity, but also provides helpful insights and answers.

Learn how MediaTek uses Cadence tools in SI design

featured paper

Designing Robust 5G Power Amplifiers for the Real World

Sponsored by Keysight

Simulating 5G power amplifier (PA) designs at the component and system levels with authentic modulation and high-fidelity behavioral models increases predictability, lowers risk, and shrinks schedules. Simulation software enables multi-technology layout and multi-domain analysis, evaluating the impacts of 5G PA design choices while delivering accurate results in a single virtual workspace. This application note delves into how authentic modulation enhances predictability and performance in 5G millimeter-wave systems.

Download now to revolutionize your design process.

featured chalk talk

GaN FETs: D-Mode Vs E-mode
Sponsored by Mouser Electronics and Nexperia
The use of gallium nitride can offer higher power efficiency, increased power density and can reduce the overall size and weight of many industrial, automotive, and data center applications. In this episode of Chalk Talk, Amelia Dalton and Giuliano Cassataro from Nexperia investigate the benefits of Gan FETs, the difference between D-Mode and E-mode GaN FET technology and how you can utilize GaN FETs in your next design.
Mar 25, 2024
4,622 views