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Astera Labs and Avery Design Partner on CXLTM 2.0 Verification for Smart Retimer Portfolio to Improve Performance in Data-Centric Applications

  • Astera Labs Aries Smart Retimers resolve signal integrity issues for high-performance server, storage, cloud and workload optimized systems
  • Avery PCIe and CXL Verification IP enabled Astera Labs to get to market faster

Tewksbury, MA., April 28, 2021 — Avery Design Systems, a leader in functional verification solutions, today announced that Astera Labs, a pioneer in connectivity solutions for intelligent systems, successfully used Avery’s Compute Express Link™ (CXLTM) 2.0 and PCI Express® (PCIe®) 5.0 Verification IP (VIP) and services in developing its Aries Smart Retimer portfolio.

The Avery CXL 2.0 and PCIe 5.0 VIP is a comprehensive solution supporting SoC verification comprised of SystemVerilog-based/UVM agents and compliance testsuites as well CXL system simulation running the latest CXL-enabled Linux kernel on QEMU-to-RTL co-simulation environment.

“The launch of our Aries CXL 2.0 Smart Retimer portfolio is a game changer for mainstreaming specialized workloads in complex heterogeneous compute and composable disaggregation system topologies,” said Kalyan Mulam, VP of Engineering, Astera Labs. “Working with a leading verification IP provider like Avery helped us streamline the design and verification process to deliver our Aries CXL 2.0 Smart Retimers to market and enable the rapidly emerging CXL ecosystem.”

“We are excited to collaborate with Astera Labs on PCIe and CXL verification of their purpose-built retimers, which play a crucial role in rapidly expanding the CXL datacenter ecosystem in 2021 and beyond,” said Chris Browy, vice president of sales and marketing at Avery Design Systems.

Availability & Additional Resources

PCIe 5.0 /6.0 and CXL VIP for CXL 2.0/1.1 is available today. 

About Avery Design Systems

Founded in 1999, Avery Design Systems, Inc. enables system and SOC design teams to achieve dramatic functional verification productivity improvements through the use of formal analysis applications for gate-level X-pessimism verification and real X root cause and sequential backtracing; and robust core-through-chip-level Verification IP for PCI Express, CXL, CCIX, Gen-Z, USB, AMBA, UFS, MIPI CSI/DSI, I3C, DDR/LPDDR, HBM, ONFI/Toggle/NOR, NVM Express, SATA, AHCI, SAS, eMMC, SD/SDIO, CAN FD, and FlexRay standards. The company has established numerous Avery Design VIP partner program affiliations with leading IP suppliers. More information about the company may be found at

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