industry news
Subscribe Now

Astera Labs and Avery Design Partner on CXLTM 2.0 Verification for Smart Retimer Portfolio to Improve Performance in Data-Centric Applications

  • Astera Labs Aries Smart Retimers resolve signal integrity issues for high-performance server, storage, cloud and workload optimized systems
  • Avery PCIe and CXL Verification IP enabled Astera Labs to get to market faster

Tewksbury, MA., April 28, 2021 — Avery Design Systems, a leader in functional verification solutions, today announced that Astera Labs, a pioneer in connectivity solutions for intelligent systems, successfully used Avery’s Compute Express Link™ (CXLTM) 2.0 and PCI Express® (PCIe®) 5.0 Verification IP (VIP) and services in developing its Aries Smart Retimer portfolio.

The Avery CXL 2.0 and PCIe 5.0 VIP is a comprehensive solution supporting SoC verification comprised of SystemVerilog-based/UVM agents and compliance testsuites as well CXL system simulation running the latest CXL-enabled Linux kernel on QEMU-to-RTL co-simulation environment.

“The launch of our Aries CXL 2.0 Smart Retimer portfolio is a game changer for mainstreaming specialized workloads in complex heterogeneous compute and composable disaggregation system topologies,” said Kalyan Mulam, VP of Engineering, Astera Labs. “Working with a leading verification IP provider like Avery helped us streamline the design and verification process to deliver our Aries CXL 2.0 Smart Retimers to market and enable the rapidly emerging CXL ecosystem.”

“We are excited to collaborate with Astera Labs on PCIe and CXL verification of their purpose-built retimers, which play a crucial role in rapidly expanding the CXL datacenter ecosystem in 2021 and beyond,” said Chris Browy, vice president of sales and marketing at Avery Design Systems.

Availability & Additional Resources

PCIe 5.0 /6.0 and CXL VIP for CXL 2.0/1.1 is available today. 

About Avery Design Systems

Founded in 1999, Avery Design Systems, Inc. enables system and SOC design teams to achieve dramatic functional verification productivity improvements through the use of formal analysis applications for gate-level X-pessimism verification and real X root cause and sequential backtracing; and robust core-through-chip-level Verification IP for PCI Express, CXL, CCIX, Gen-Z, USB, AMBA, UFS, MIPI CSI/DSI, I3C, DDR/LPDDR, HBM, ONFI/Toggle/NOR, NVM Express, SATA, AHCI, SAS, eMMC, SD/SDIO, CAN FD, and FlexRay standards. The company has established numerous Avery Design VIP partner program affiliations with leading IP suppliers. More information about the company may be found at www.avery-design.com.

Leave a Reply

featured blogs
May 12, 2021
The ICADVM20.1 ISR18 and IC6.1.8 ISR18 production releases are now available for download at Cadence Downloads . For information on supported platforms and other release compatibility information,... [[ Click on the title to access the full blog on the Cadence Community site...
May 11, 2021
Human vision in indispensable and often taken for granted. Similarly machine, or embedded, vision influences daily human life in ways thought impossible. Simply, machine vision refers to the ability of embedded systems to “see”. Key system components include camer...
May 6, 2021
Learn how correct-by-construction coding enables a more productive chip design process, as new code review tools address bugs early in the design process. The post Find Bugs Earlier Via On-the-Fly Code Checking for Productive Chip Design and Verification appeared first on Fr...
May 4, 2021
What a difference a year can make! Oh, we're not referring to that virus that… The post Realize Live + U2U: Side by Side appeared first on Design with Calibre....

featured video

Insights on StarRC Standalone Netlist Reducer

Sponsored by Synopsys

With the ever-growing size of extracted netlists, parasitic optimization is key to achieve practical simulation run times. Key trade-off for any netlist reducer is accuracy vs netlist size. StarRC Standalone Netlist reducer provides the flexibility to optimize your netlist on a per net basis. The user has total control of trading accuracy of some nets versus netlist optimization - yet another feature from StarRC to provide flexibility to the designer.

Click here for more information

featured paper

E-book: An engineer’s guide to autonomous and collaborative industrial robots

Sponsored by Texas Instruments

As robots are becoming more commonplace in factories, it is important that they become more intelligent, autonomous, safer and efficient. All of this is enabled with precise motor control, advanced sensing technologies and processing at the edge, all with robust real-time communication. In our e-book, an engineer’s guide to industrial robots, we take an in-depth look at the key technologies used in various robotic applications.

Click to download e-book

featured chalk talk

Medical Device Security

Sponsored by Siemens Digital Industries Software

In the new era of connected medical devices, securing embedded systems has become more important than ever. But, there is a lot medical device designers can borrow from current best-practices for embedded security in general. In this episode of Chalk Talk, Amelia Dalton chats with Robert Bates from Mentor about strategies and challenges for securing modern medical devices and systems.

Click here to download a whitepaper called "Medical Device Security: Achieving Regulatory Approval"