industry news
Subscribe Now

Aldec Adds Customizable Tool Qualification Data Package to ALINT-PRO™ for DO-254 Projects

Henderson, NV, USA – June 30, 2020 – Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, has added a customizable tool qualification data package to ALINT-PRO™ to save users considerable time when qualifying the tool’s use in projects requiring Design Assurance Levels (DAL) A and B under DO-254 guidance.

Avionics system manufacturers using complex devices such as FPGAs must meet specific RTCA/DO-254 process objectives in order to receive system approval. DO-254 recommends that applicants define and follow HDL coding standards commensurate to the complexity of the FPGA design. It is allowed, and even suggested by the DO-254 Users Group, that linting tools be used to enforce HDL coding standards automatically. Using such tools makes the design review more effective, more reliable, and much faster.

The only requirement for DAL A and B is that the user must prove verification tools such as linters will detect errors in the design and functionally behave as intended. Following the Tool Assessment and Qualification process described under RTCA/DO-254 guidance, Aldec has enabled users to implement and run the Basic Tool Qualification process.

Aldec now offers the complete and customizable qualification package for the Basic Tool Qualification process.

The data package is customizable which means it is prepared to satisfy user requirements and proves that ALINT-PRO can enforce the user’s chosen coding standard, either the one included in ALINT-PRO or one the user has mapped into the tool. The package includes an automated test suite and comprehensive documentation. The only work the user need do is to run the test suite in its intendent environment and complete the documentation with tests result and environment information.

“This Qualification Package should greatly accelerate an applicant’s performance of the DO-254-required Basic Tool Qualification for ALINT-PRO,” comments Tom Ferrell, Consulting FAA Designated Engineering Representative (DER). “The rule-based tests are clearly defined and the flexibility built-in to the tool allows for clean and concise alignment to an applicant’s coding standard. Overall, a great addition to the DO-254 tool space.”

Janusz Kitel, DO-254 Program Manager at Aldec, adds: “One of the most significant benefits of using ALINT-PRO to enforce coding standard is the huge amount of time saved when compared to performing a manual review. However, we want to save the user even more time, by not having to manually prove the tool works correctly, which can take a significant amount of time.”

Aldec continues to support DO-254 users in this area by providing the independent assessment path and tool qualification data packages for all of its tools used for DO-254 compliance including code coverage, HDL simulation, hardware test platforms and now linting with best-practice HDL coding standards.

“As a verification company we have always recognized the importance of verifying that our verification tools perform as intended,” concludes Kitel, “and the ability to prove and record that has always been present, though requiring a series of manual activities. Conscious of how precious time is for engineers working on projects requiring DO-254 certification and recognizing that tool qualification may be a necessary but time-consuming activity, we believe our qualification packages are of great benefit.”

About ALINT-PRO

ALINT-PRO™ is a design verification solution for RTL code written in VHDL, Verilog and SystemVerilog, which is focused on verifying coding style and naming conventions, RTL and post-synthesis simulation mismatches, smooth and optimal synthesis, avoiding problems on further design stages, clocks and reset tree issues, CDC, DFT, and coding for portability and reuse. The solution performs static analysis based on RTL and SDC™ source files uncovering critical design issues early in the design cycle, which in turn reduces design signoff time dramatically.

About Aldec

Aldec Inc., headquartered in Henderson, Nevada, is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, SoC and ASIC Prototyping, Design Rule Checking, CDC Verification, IP Cores, Requirements Lifecycle Management, DO-254 Functional Verification and Military/Aerospace solutions. www.aldec.com

Leave a Reply

featured blogs
Jul 3, 2020
[From the last episode: We looked at CNNs for vision as well as other neural networks for other applications.] We'€™re going to take a quick detour into math today. For those of you that have done advanced math, this may be a review, or it might even seem to be talking down...
Jul 2, 2020
Using the bitwise operators in general -- and employing them to perform masking, bit testing, and bit setting/clearing operations in particular -- can be extremely efficacious....
Jul 2, 2020
In June, we continued to upgrade several key pieces of content across the website, including more interactive product explorers on several pages and a homepage refresh. We also made a significant update to our product pages which allows logged-in users to see customer-specifi...

Featured Video

Product Update: DesignWare® TCAM IP -- Synopsys

Sponsored by Synopsys

Join Rahul Thukral in this discussion on TCAMs, including performance and power considerations. Synopsys TCAMs are used in networking and automotive applications as they are low-risk, production-proven, and meet automotive requirements.

Click here for more information about DesignWare Foundation IP: Embedded Memories, Logic Libraries & GPIO

Featured Paper

Cryptography: A Closer Look at the Algorithms

Sponsored by Maxim Integrated

Get more details about how cryptographic algorithms are implemented and how an asymmetric key algorithm can be used to exchange a shared private key.

Click here to download the whitepaper

Featured Chalk Talk

SLX FPGA: Accelerate the Journey from C/C++ to FPGA

Sponsored by Silexica

High-level synthesis (HLS) brings incredible power to FPGA design. But harnessing the full power of HLS with FPGAs can be difficult even for the most experienced engineering teams. In this episode of Chalk Talk, Amelia Dalton chats with Jordon Inkeles of Silexica about using the SLX FPGA tool to truly harness the power of HLS with FPGAs, getting better results faster - regardless of whether you are approaching from the hardware or software domain.

More information about SLX FPGA