Düsseldorf, July 22, 2015 – Renesas Electronics, a premier supplier of advanced semiconductor solutions, today announced the release of two new series of Advanced Low Power SRAM (Advanced LP SRAM), the leading type of low-power-consumption SRAM, designed to provide enhanced reliability and longer backup battery life for applications such as factory automation (FA), industrial equipment, and the smart grid. Fabricated using the 110-nanometer (nm) process, the new RMLV1616A Series of 16-megabit (Mb) devices and the RMWV3216A Series of 32 Mb devices feature an innovative memory cell technology that dramatically improves reliability and contributes to longer battery operation.
The recent demands for highly secure and reliable user systems are driving increased demand for highly reliable SRAM, which is used to store important information such as system programs and financial transaction data. The prevention of soft errors (Note 1) caused by alpha rays and cosmic neutron rays is a significant issue. Typical measures to deal with this problem include embedding an error correcting code (ECC) circuit in the SRAM or user system to correct any soft errors that occur. There are limits, however, to the error correction capabilities of ECC circuits. For example, some cannot correct simultaneous errors affecting multiple bits.
Renesas’ Advanced LP SRAM devices feature exclusive technology in their memory cells that achieves soft error resistance (Note 2) over 500 times that of conventional Full CMOS memory cells (Note 3). This makes it desirable for use in fields requiring high reliability, including FA, measurement devices, smart grid-related devices, and industrial equipment, in addition to many other fields, such as consumer devices, office equipment, and communication devices.
Highlights of the new RMLV1616A Series and RMWV3216A Series features:
(1) Renesas’ exclusive Advanced LP SRAM technology for dramatically better soft error resistance and enhanced reliability
In the Renesas Advanced LP SRAM structure, a stacked capacitor (Note 4) is added to each memory node (Note 5) within the memory cells. This configuration suppresses the generation of soft errors to a level that is effectively soft error free (Note 6). In addition, the load transistor (P-channel) of each SRAM cell is a polysilicon thin-film transistor (TFT) (Note 7) that is stacked on top of the N-channel MOS transistor formed on the silicon. Only the N-channel MOS transistor is formed on the silicon substrate below. This means that no parasiticthyristors are formed in the memory area and theoretically makes latch-up (Note 8) impossible. Therefore, the Advanced LP SRAM is well suited to applications requiring high reliability, such as FA, measurement devices, smart grid related devices, traffic systems, and industrial equipment.
(2) Reduction of standby current to less than half the earlier level for longer backup battery service life
The standby current of the new RMLV1616A Series and RMWV3216A Series is only 0.5 microamperes (?A) (typical) for 16 Mb devices and 1 ?A (typical) for 32 Mb devices (Note 9). These low current consumption levels are less than half the levels of comparable earlierRenesas SRAM products (Note 10), making it possible to extend the service life of backup batteries. The minimum power supply voltage when retaining data is 1.5 V, lower than the 2.0 V of comparable earlier Renesas products. This helps customers designing systems that retain data using battery power.
(3) Package lineup
The 16 Mb RMLV1616A Series is available in three packages: 48-ball FBGA, 48-pin TSOP (I), and 52-pin ?TSOP (II), allowing customers to select the package that best matches their application. The 32 Mb RMWV3216A Series is available in a 48-ball FBGA package.
Refer to the separate sheet for the main specifications of the new RMLV1616A Series and RMWV3216A Series.
Availability
Samples of the RMLV1616A Series and RMWV3216A Series will be available in September. Mass production of the two series is scheduled to begin in October 2015. Mass production using the 110 nm process has already begun for Advanced LP SRAM products with 4 Mbit and 8 Mbit capacities.
(Note 1) Soft errors:
A phenomenon that occurs when alpha rays and cosmic neutron rays from external sources impinge on the silicon substrate, generating an electric charge within the substrate that causes information stored in the memory to be lost. In contrast to hard errors such as physical faults in the semiconductor elements, which are reproducible, soft errors are not reproducible, so the system can restore the original state simply by rewriting the data. Generally speaking, the rate of soft errors increases as the fabrication process becomes more ultrafine.
(Note 2) Based on system soft error evaluations performed by Renesas.
(Note 3) Full CMOS memory cells:
A SRAM memory cell configuration in which a total of six P-channel MOS transistor and N-channel MOS transistor elements are formed on the same plane of the silicon substrate. The surface area is large and there is a latch-up risk.
(Note 4) Stacked capacitor:
Capacitors with two electrodes formed from polysilicon or metal. These capacitors are formed on the upper layer of the MOS transistors on the silicon substrate.
(Note 5) Memory node:
Flip-flop circuit nodes within each memory cell that store bits of information as “high” or “low” electric potential.
(Note 6) Renesas has published on its website the results of its evaluations of soft errors in systems employing Advanced LP SRAM. These evaluations were run for more than a year under conditions similar to the usage environment of average users, and in the end no errors were detected. See the following URL for details:
http://www.renesas.com/products/memory/low_power_sram/child/renesas_effort.jsp
(Note 7) Thin-film transistor (TFT):
A transistor formed from thin-film polysilicon. Such elements are used as the SRAM load transistors, formed on the top layer of the MOS transistors on the silicon substrate.
(Note 8) Latch-up:
A phenomenon in which an NPN or PNP structure (parasitic bipolar transistor) formed by the well, silicon substrate, P-type diffusion layer, and N-type diffusion layer of a CMOS transistor enters the on state due to overvoltage from the power supply or input pins, allowing a large current to flow between the power supply and ground.
(Note 9) Reference values at a power supply voltage of 3.0 V and ambient temperature of 25°C.
(Note 10) The R1LV1616R Series and R1WV3216R Series, which employ the 150 nm process.
About Renesas Electronics Europe
Renesas Electronics is the world’s number one supplier of microcontrollers and a premier supplier of advanced semiconductor solutions, including system-on-chip and a wide range of discrete analogue and power devices. Established in 2010, Renesas Electronics combines the collective semiconductor expertise of Hitachi, Mitsubishi Electric and NEC Electronics, encapsulating more than 200 years’ experience.
Renesas’ products are the result of decades of research and investment into semiconductor technology and customer solutions. Today, they provide pioneering platforms for the advancement of the Smart Society, embedding intelligence, connectivity, safety and security in solutions for cars, homes, buildings and factories. In Europe, Renesas complements its cutting-edge technology with resources that foster customer proximity and span the entire product lifecycle. These include the European Technology Centre, which designs innovative solutions specifically for Europe, and the European Quality Centre in Düsseldorf, which provides technical support to customers throughout the region. Renesas also operates an effective ecosystem, comprising the industry’s largest local support network and an extensive network of over 800 hardware and software alliance partners.
Headquartered in Japan, Renesas Electronics has subsidiaries in 20 countries worldwide. More information is available atwww.renesas.eu.
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