industry news
Subscribe Now

Synopsys and TSMC Collaborate to Develop Integrated IoT Platform for TSMC 40-nm Ultra-Low-Power Process

MOUNTAIN VIEW, Calif., June 8, 2015 /PRNewswire/ —


  • Platform includes pre-verified sensor and control IP subsystem with ARC EM5D processor as well as logic libraries, memory compilers, NVM, MIPI, USB and ADC
  • Thick-oxide logic libraries and low voltage memories minimize leakage current
  • Hardware accelerators and bus-less processor architecture reduces area and cycle count for always-on functions such as sensor fusion and voice recognition
  • embARC Open Software Platform provides online access to free and open source drivers, operating systems and middleware for software developers implementing ARC processor-based designs

Synopsys, Inc. (Nasdaq:SNPS) today announced a collaboration with TSMC to develop an integrated Internet of Things (IoT) platform on TSMC’s 40-nm ultra-low-power (ULP) process technology. The IoT platform incorporates a broad range of DesignWare® IP, including an integrated sensor and control IP subsystem with the ultra-low-power ARC® EM5D processor core, power-and area-optimized logic libraries, memory compilers, NVM, MIPI and USB interfaces as well as an analog-to-digital converter (ADC). The high-performance, low-power IoT platform provides designers with a pre-validated solution that enables them to deliver the energy-efficient, always-on processing required for applications such as sensor fusion and voice recognition.

The ability to capture information from multiple sensors, perform something “smart” with that information and relay these results to the cloud is driving IoT application innovation, particularly in the wearable and machine-to-machine markets. Synopsys provides a comprehensive portfolio of DesignWare IP that meets the specific requirements of IoT system-on-chip (SoC) designs including:

  • Pre-validated hardware and software sensor and control IP subsystem that delivers significant area and power savings with lower system-level latency. The subsystem provides orders of magnitude reduction in cycle count because of a bus-less architecture and area-efficient hardware accelerators.
  • Power-efficient ARC EM5D processor core featuring a comprehensive set of RISC and DSP instructions and customizable hardware extensions
  • Area-optimized interface IP, including silicon-proven USB with battery-charging and power-down features
  • Power optimization kits and ultra-high density logic libraries with multi-bit flip-flops minimize power and area, while compatible thick oxide libraries deliver low leakage for always-on functions
  • High-density, low voltage memory compilers incorporate the smallest TSMC bit cells with integrated test and repair supporting embedded flash

Synopsys embARC Open Software Platform gives ARC software developers online access to a comprehensive suite of free and open-source software that eases the development of code for the IoT and other embedded applications. embARC includes commonly used components for the IoT, such as MQTT and CoAP internet protocols as well as FreeRTOS and Contiki OS operating systems.

“TSMC’s long collaboration with Synopsys has enabled us to provide our mutual customers with access to a broad portfolio of high-quality IP on a broad range of TSMC process technologies for their target applications,” said TSMC Senior Director, Design Infrastructure Marketing Division, Suk Lee.  “This IoT platform will help designers take advantage of TSMC’s 40-nm ULP process and quickly ramp into volume production for the rapidly expanding IoT market.” 

“Synopsys has optimized a broad portfolio of IP for TSMC’s 40-nm ultra-low-power process targeting energy-efficient IoT designs,” said John Koeter, vice president of marketing for IP and prototyping at Synopsys. “By collaborating with TSMC on the IoT platform we’ve enabled designers to meet aggressive power and cost goals, while accelerating their project schedules in this fast-moving market.”


Learn more about DesignWare IP solutions for the IoT:

Learn more about the embARC Open Software Platform:

About DesignWare IP

Synopsys is a leading provider of high-quality, silicon-proven IP solutions for SoC designs. The broad DesignWare IP portfolio includes complete interface IP solutions consisting of controller, PHY and next-generation verification IP, analog IP, embedded memories, logic libraries, processor solutions and subsystems. To accelerate prototyping, software development and integration of IP into SoCs, Synopsys’ IP Accelerated initiative offers IP prototyping kits, IP software development kits and customized IP subsystems for rapid integration of IP into SoCs. Synopsys’ extensive investment in IP quality, comprehensive technical support and robust IP development methodology enables designers to reduce integration risk and accelerate time-to-market. For more information on DesignWare IP, visit

About Synopsys

Synopsys, Inc. (Nasdaq:SNPS) is the Silicon to Software partner for innovative companies developing the electronic products and software applications we rely on every day. As the world’s 15th largest software company, Synopsys has a long history of being a global leader in electronic design automation (EDA) and semiconductor IP, and is also a leader in software quality and security testing with its Coverity® solutions. Whether you’re a system-on-chip (SoC) designer creating advanced semiconductors, or a software developer writing applications that require the highest quality and security, Synopsys has the solutions needed to deliver innovative, high-quality, secure products. Learn more at

Leave a Reply

featured blogs
Jan 21, 2022
Here are a few teasers for what you'll find in this week's round-up of CFD news and notes. How AI can be trained to identify more objects than are in its learning dataset. Will GPUs really... [[ Click on the title to access the full blog on the Cadence Community si...
Jan 20, 2022
High performance computing continues to expand & evolve; our team shares their 2022 HPC predictions including new HPC applications and processor architectures. The post The Future of High-Performance Computing (HPC): Key Predictions for 2022 appeared first on From Silico...
Jan 20, 2022
As Josh Wardle famously said about his creation: "It's not trying to do anything shady with your data or your eyeballs ... It's just a game that's fun.'...

featured video

Synopsys & Samtec: Successful 112G PAM-4 System Interoperability

Sponsored by Synopsys

This Supercomputing Conference demo shows a seamless interoperability between Synopsys' DesignWare 112G Ethernet PHY IP and Samtec's NovaRay IO and cable assembly. The demo shows excellent performance, BER at 1e-08 and total insertion loss of 37dB. Synopsys and Samtec are enabling the industry with a complete 112G PAM-4 system, which is essential for high-performance computing.

Click here for more information about DesignWare Ethernet IP Solutions

featured paper

Enhancing PSAP Audio Performance and Power Efficiency in Hearables with Anti-Noise

Sponsored by Analog Devices

PSAP enhances user's listening experiences with hearables in challenging environments. Long delay in the audio system creates distortion known as comb effect in PSAP. This paper investigates the root cause of the comb effect and explains how a new anti-noise device yields a superior system performance compared to conventional PSAP solutions.

Click here to read more

featured chalk talk

RF Interconnect for Automotive Applications

Sponsored by Mouser Electronics and Amphenol RF

Modern and future automotive systems will put enormous demands on RF. We need reliable, high-bandwidth, low-latency, secure wireless connections between cars and infrastructure, from car to car, and within systems on each car. In this episode of Chalk Talk, Amelia Dalton chats with Owen Barthelmes and Kelly Freeman of Amphenol RF to talk about interconnects for these new, challenging automotive RF systems.

Click here for more information