industry news
Subscribe Now

Cadence Expands ARM-based System Verification Solution, Reducing Time-to-Market for Mobile, Networking and Server Applications

Highlights:

  • Cadence speeds up and expands Interconnect Workbench solution for ARM® CoreLink™ 400 interconnect IP-based systems to deliver faster performance verification and analysis
  • Cadence now provides ARM Fast Models combined with the Palladium® XP II platform to support ARMv8-based system embedded OS verification
  • Verification IP supporting the ARM AMBA® 5 CHI protocol for advanced networking, storage and server systems is now available for simulation and the Palladium XP II platform

SAN JOSE, Calif., March 12, 2014—Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced an expansion of its ARM-based design system verification solution in order to drive shorter time-to-market for mobile, networking and server applications. This expanded solution from Cadence features several enhancements and speeds system design and early software development for ARM Cortex®-A processor series based systems.

In collaboration with ARM, Cadence enhanced its System Development Suite’s ARM-based system verification solution by including:

  • New adaptable interconnect performance characterization test suite in the Cadence® Interconnect Workbench, along with AMBA Designer integration, that delivers a significant speed-up of performance analysis and verification of CoreLink CCI-400 system IP and NIC-400 design tool based systems.
  • Expanded and pre-verified support of hardware-accurate OS embedded software verification using Palladium XP II platform with ARMv8 64-bit Cortex processor family Fast Models, which are now available through Cadence.
  • Verification IP supporting AMBA 5 Coherent Hub Interface (CHI) protocol is the same protocol as implemented in the ARM CoreLink CCN-508 system IP and silicon proven CoreLink CCN-504 Cache Coherent Networks as used in enterprise level applications. The new Verification IP runs on all industry simulators, plus Accelerated Verification IP for Palladium XP II platforms.

“In the ultra-competitive mobile, network and server markets, our partners are driven by the need to quickly differentiate and deliver the right product inside very tight development windows” said James McNiven, deputy general manager, systems & software group, ARM.  “The expanding collaboration between ARM and Cadence, and the availability of better ARM-based system design and verification automation, enables our joint partners to focus on innovation and getting their value added products to market faster.”

“The Cadence Palladium solution for embedded software development enabled by ARM-based Fast Models helps us reduce the system software validation cycle and ensures a smoother post-silicon bring-up,” said Kevin Kranzusch, vice president, System Software, at NVIDIA. “The continued delivery of innovating technology from ARM and Cadence is crucial to our ongoing success.”

For more information on this solution visit www.cadence.com/news/sds

About Cadence

Cadence enables global electronic design innovation and plays an essential role in the creation of today’s integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available here.

Leave a Reply

featured blogs
Apr 23, 2024
The automotive industry's transformation from a primarily mechanical domain to a highly technological one is remarkable. Once considered mere vehicles, cars are now advanced computers on wheels, embodying the shift from roaring engines to the quiet hum of processors due ...
Apr 22, 2024
Learn what gate-all-around (GAA) transistors are, explore the switch from fin field-effect transistors (FinFETs), and see the impact on SoC design & EDA tools.The post What You Need to Know About Gate-All-Around Designs appeared first on Chip Design....
Apr 18, 2024
Are you ready for a revolution in robotic technology (as opposed to a robotic revolution, of course)?...

featured video

MaxLinear Integrates Analog & Digital Design in One Chip with Cadence 3D Solvers

Sponsored by Cadence Design Systems

MaxLinear has the unique capability of integrating analog and digital design on the same chip. Because of this, the team developed some interesting technology in the communication space. In the optical infrastructure domain, they created the first fully integrated 5nm CMOS PAM4 DSP. All their products solve critical communication and high-frequency analysis challenges.

Learn more about how MaxLinear is using Cadence’s Clarity 3D Solver and EMX Planar 3D Solver in their design process.

featured chalk talk

SLM Silicon.da Introduction
Sponsored by Synopsys
In this episode of Chalk Talk, Amelia Dalton and Guy Cortez from Synopsys investigate how Synopsys’ Silicon.da platform can increase engineering productivity and silicon efficiency while providing the tool scalability needed for today’s semiconductor designs. They also walk through the steps involved in a SLM workflow and examine how this open and extensible platform can help you avoid pitfalls in each step of your next IC design.
Dec 6, 2023
18,409 views