industry news
Subscribe Now

Jasper and Duolog Partner to Combine SoC Integration with Formal Verification

May 30, 2013, MOUNTAIN VIEW, Calif. — Jasper Design Automation, Inc., the leading provider of verification solutions based on state-of-the-art formal technology, and Duolog Technologies, the leading provider of SoC integration products and solutions, have announced a partnership to leverage the tools and methodologies of both companies. The companies’ integrated solutions will address the complex, time-consuming and error-prone tasks associated with SoC integration and verification. The integrated flows by Duolog and Jasper will enable IP/SoC development teams to deliver qualified, integration-ready IP and SoC assembly that is seamlessly verified using formal verification methods. The combined solutions provide accelerated and continuous SoC integration, offering significant improvements in both productivity and quality of results (QoR).

“ARM delivers packaged and verified IP that enables our customers to meet their design targets with reduced risk,” said John Goodenough, vice president of Design Technology and Automation, ARM.  “Duolog and Jasper have been valued partners providing IP integration and verification tools and flows for these mission-critical processes. The new, integrated flows from the two companies should both increase productivity and quality for us and for our customers.”

Breaking New Ground: Combining IP Integration and Verification Flows

The combined Duolog and Jasper flows will enable design teams to quickly and accurately identify issues, inconsistencies and omissions when assembling complex IP-based systems. The integrated design flows enable designers to work from black-box system specifications, through design capture and integration, to verification. Teams can verify the correctness of both the specification and the implementation, while also detecting gaps in the specification.

The partnership will initially deliver two flows. The first will focus on the capture and verification of register metadata, combining Duolog’s Socrates Bitwise register management tool with the JasperGold® Control and Status Register (JG-CSR) Verification App. The flow will enable IP designers to verify both executable specifications and RTL for consistency and completeness.

The second flow leverages Duolog’s Socrates Weaver SoC integration tool and the JasperGold Connectivity Verification App (JG-CONN). This flow will enable SoC design teams to assemble, construct and exhaustively verify a complete SoC integration, including temporal and conditional connections, as well as multiplexed IO connections.

Duolog’s and Jasper’s solutions utilize the IEEE1685 IP-XACT standard as a robust data exchange format to seamlessly exchange metadata among the different tools and enable these joint flows. With ARM IP being packaged using IP-XACT, Duolog and Jasper’s solutions are 100% interoperable with ARM IP enabling a fully automated methodology and flow.

“Getting from a specification to complete and verified SoC integration is a tedious, repetitive cycle of modification and verification,” said Norman Walsh, COO of Duolog. “The Duolog/Jasper partnership will transform this into a highly effective cycle of continuous integration and verification that will have a significant positive impact on both SoC quality and time-to-market.”

“The two companies’ solutions are more than complementary — they are an ideal fit,” said Oz Levia, Vice President of Marketing and Business Development, Jasper Design Automation. “The integrated design flow is very intuitive, from black-box system specifications, through design capture and integration, to verification. And the Duolog/Jasper partnership will assure ongoing compatibility of our tools and technology roadmaps.”

The integrated solutions will be demonstrated at the Design Automation Conference in Austin TX, June 3-5, 2013. Demonstrations of the flows, the use methodology and the related benefits will be available at both the Jasper booth (#2346) and the adjacent Duolog booth (#2246).  The companies will also host a joint seminar at DAC with ARM in their respective booths.  To register for a seminar, visit http://www.jasper-da.com/Jasper_at_DAC_2013.

Availability

The new flows are available now. For pricing and sales inquiries please contact: Duolog Technologies atsales@duolog.com; Jasper Design Automation at info@jasper-da.com.

About Socrates

Socrates is a standards-based platform for modeling SoC metadata, simplifying and formalizing flows and automating flow steps. Socrates hosts a number of flow automation applications that simplify and accelerate the SoC assembly process, including Socrates 1685 IP-XACT (IEEE-1685) design environment, Socrates Bitwise register and memory-map management, Socrates Weaver rules-based connectivity engine and Socrates Spinner IO layer specification and generation. In addition to the standard Socrates applications, customers and partners can develop their own applications and flows on Socrates, even incorporating legacy or third-party scripts and utilities. The power and flexibility of Socrates offers methodology and development teams a scalable path to rapid, reliable and repeatable SoC assembly.

About Duolog Technologies

Duolog Technologies is a leading developer of EDA products that address the increasingly complex challenges of SoC integration.  We enable our customers to deliver integrated systems more quickly and cost effectively than their competitors.  Our innovative tools and solutions allow for maximum productivity and control throughout the entire SoC lifecycle.

About JasperGold Apps

JasperGold Apps are built on a single platform that combines multiple formal-based solutions and leverages a common shared database and user interface.  The Apps architecture enables sharing of design and verification data for each design under test (DUT) between Apps for increased consistency and productivity.  The Apps architecture supports deployment of multiple Apps simultaneously as well as multiple invocations of the same App for improved throughput and performance. 

The Apps architecture is extensible such that customers can take advantage of future Apps that will address emerging design and verification needs.  The design and verification challenges that customers have addressed by creating flows using our formal technology have been the inspiration for several Apps.  Customers will be able to continue to leverage the powerful and highly programmable platform in JasperGold to develop their customized flows.

About Jasper Design Automation

Jasper Design Automation delivers industry-leading software solutions for semiconductor design, verification, and Intellectual Property (IP) reuse, based on state-of-the-art formal technology.  Customers include worldwide leaders in the wireless, consumer, computing, and networking electronics industries. Jasper technology has been an essential part of 150 plus successful chip deployments.  Headquartered in Mountain View, California, the company is privately held, with offices and distributors in North America, South America, Europe, Israel, and Asia.  Visit www.jasper-da.comto reduce risks, increase design, verification and reuse productivity and accelerate time to market.

Leave a Reply

featured blogs
May 22, 2020
As small as a postage stamp, the Seeeduino XIAO boasts a 32-bit Arm Cortex-M0+ processor running at 48 MHz with 256 KB of flash memory and 32 KB of SRAM....
May 22, 2020
Movies have the BAFTAs and Academy Awards. Music has the GRAMMYs. Broadway has the Tonys. Global footballers have the Ballon d’Or. SI/PI engineers have the DesignCon 2020 Best Paper Award? Really? What’s that? Many people are familiar with annual awards mentioned....
May 22, 2020
[From the last episode: We looked at the complexities of cache in a multicore processor.] OK, time for a breather and for some review. We'€™ve taken quite the tour of computing, both in an IoT device (or even a laptop) and in the cloud. Here are some basic things we looked ...
May 21, 2020
In this time of financial uncertainty, a yield-shield portfolio can protect your investments from market volatility.  Uncertainty can be defined as a quantitative measurement of variability in the data [1]. The more the variability in the data – whet...

Featured Video

Featured Paper

Automatic Test Equipment Guide

Sponsored by Maxim Integrated

This application note provides a solution for understanding and design of ATE testers with complex functionality by describing major blocks of pin electronics (PE) devices and depicting different tester architectures.

Click here to download the whitepaper