industry news
Subscribe Now

Altera Stratix V GX FPGAs Achieve PCIe Gen3 Compliance and Listing on PCI-SIG Integrators List

San Jose, Calif., May 21, 2013—Altera Corporation (NASDAQ: ALTR) today announced its 28 nm Stratix® V GX FPGAs have achieved inclusion on the latest PCI-SIG® Integrators List for the PCI Express® (PCIe®) 3.0 specification (Gen3).  At the most recent PCI-SIG workshop, Stratix V GX FPGAs successfully passed all PCI-SIG compliance and interoperability tests, completing inclusion for Stratix V on all three generations of the Integrators Lists for PCIe. With Cyclone V and Arria V devices included on the 1.1 (Gen 1) and 2.0 (Gen2) lists, Altera’s entire 28 nm portfolio is now certified by the PCI-SIG as PCIe compliant at all three generations.

Also announced today is Altera’s direct memory access (DMA) reference design, constructed for Stratix V customers needing to seamlessly and quickly design PCIe Gen3 solutions. Stratix V GX FPGAs feature a hardened protocol stack for PCIe Gen3 applications, demanding the highest in bandwidth, system integration and flexibility, at a reduced cost with lower total power consumption.

“The inclusion of the Stratix V FPGA’s on the first ever PCIe Gen 3 Integrators List is a significant accomplishment for our high-performance devices,” said Patrick Dorsey, senior director of Product Marketing, Altera. “Customers needing the performance of Stratix V and PCIe Gen3 can now design systems with the confidence that the two will seamlessly work together. Additionally, our new DMA reference design makes it fast and easy to develop high-performance PCIe Gen3x8 hardware.”

The Altera DMA reference design highlights the capabilities of Stratix V designs that require PCIe Gen3x8. By demonstrating peak bandwidth of the theoretical maximum, the reference design shows that Altera’s Gen3 solution can preserve almost all the bandwidth available in Gen3 systems or at Gen3 data rates. Also, by demonstrating simultaneous read/write at upwards of 11 GB/sec, the design shows how much bandwidth customers can take advantage of in a real-world implementation. Features of the DMA reference design include:

  • Linux driver that works with the example design
  • Peak throughput (142 cycles of 256-bit at 250MHz)
  • 7.1 GB/s : back to back Tx Memory Write 256 Byte payload
  • 7.0 GB/s : back to back Rx Read Completion Throughput
  • Simultaneous read/write : 11.4GB/sec

Altera Stratix V GX FPGAs for PCIe Gen3

Stratix V FPGAs feature up to four hard PCIe Gen3x8 intellectual property (IP) blocks. The PCIe Gen3 IP blocks support x1, x2, x4 and x8 lane configurations and provide transfer rates up to 8-Gbps per lane, sustaining 2x higher throughput using Gen3 x8 lanes compared to the previous Gen2 x8 version. Hardening the PCIe IP blocks in Stratix V FPGAs delivers a savings of up to 100,000 logic elements when compared to alternative soft implementations. The hard PCIe Gen3 IP blocks embed the PCIe protocol stack into the FPGA and include the transceiver modules, physical layer, data link layer and transaction layer. Stratix V FPGA’s PCIe Gen3 IP targets PCIe Base Specification Rev. 3.0, 2.x, and 1.x.

Altera offers a full spectrum of PCI-SIG-compliant solutions across its entire product portfolio that are optimized the meet key application requirements. These solutions include configurable PCIe IP cores and development boards for endpoint, bridge, switch and root port functionalities.

Availability

Altera Stratix V GX FPGAs are currently in production shipping. The DMA reference design is available for download in the Quartus® II software version 13.0. For further questions or ordering information, contact your local Altera sales representative or authorized distributor.

About Altera

Altera® programmable solutions enable designers of electronic systems to rapidly and cost effectively innovate, differentiate and win in their markets. Altera offers FPGAs, SoCs, CPLDs, and ASICs in combination with software tools, intellectual property, embedded processors and customer support to provide high-value programmable solutions to customers worldwide. Follow Altera via Facebook, Twitter, LinkedIn, Google+ and RSS, and subscribe to product update emails and newsletters.  altera.com

Leave a Reply

featured blogs
May 8, 2024
Learn how artificial intelligence of things (AIoT) applications at the edge rely on TSMC's N12e manufacturing processes and specialized semiconductor IP.The post How Synopsys IP and TSMC’s N12e Process are Driving AIoT appeared first on Chip Design....
May 2, 2024
I'm envisioning what one of these pieces would look like on the wall of my office. It would look awesome!...

featured video

Why Wiwynn Energy-Optimized Data Center IT Solutions Use Cadence Optimality Explorer

Sponsored by Cadence Design Systems

In the AI era, as the signal-data rate increases, the signal integrity challenges in server designs also increase. Wiwynn provides hyperscale data centers with innovative cloud IT infrastructure, bringing the best total cost of ownership (TCO), energy, and energy-itemized IT solutions from the cloud to the edge.

Learn more about how Wiwynn is developing a new methodology for PCB designs with Cadence’s Optimality Intelligent System Explorer and Clarity 3D Solver.

featured paper

Achieve Greater Design Flexibility and Reduce Costs with Chiplets

Sponsored by Keysight

Chiplets are a new way to build a system-on-chips (SoCs) to improve yields and reduce costs. It partitions the chip into discrete elements and connects them with a standardized interface, enabling designers to meet performance, efficiency, power, size, and cost challenges in the 5 / 6G, artificial intelligence (AI), and virtual reality (VR) era. This white paper will discuss the shift to chiplet adoption and Keysight EDA's implementation of the communication standard (UCIe) into the Keysight Advanced Design System (ADS).

Dive into the technical details – download now.

featured chalk talk

Optimize Performance: RF Solutions from PCB to Antenna
Sponsored by Mouser Electronics and Amphenol
RF is a ubiquitous design element found in a large variety of electronic designs today. In this episode of Chalk Talk, Amelia Dalton and Rahul Rajan from Amphenol RF discuss how you can optimize your RF performance through each step of the signal chain. They examine how you can utilize Amphenol’s RF wide range of connectors including solutions for PCBs, board to board RF connectivity, board to panel and more!
May 25, 2023
40,338 views