industry news
Subscribe Now

Multicore Association Unveils Specification to Ease Programming of SoCs

El Dorado Hills, Calif. – Feb. 22, 2013 – After 1.5 years of working-group effort, the Multicore Association™, a global non-profit organization that develops standards to speed time-to-market for products with multicore processor implementations, has announced the availability of its Multicore Task Management Application Program Interface (MTAPI) that supports the coordination of tasks on embedded parallel systems.

To fully utilize homogeneous and/or heterogeneous multicore processors or systems-on-chip (SoCs), a programmer must develop software that splits a program into tasks that can be executed concurrently on different processor cores.  Today’s operating systems and runtime libraries for embedded systems provide threads or thread-like mechanisms that are not suited for the fine-grain parallelism required by multicore architectures, typically because the coordination of hundreds or thousands of parallel tasks generates too much overhead relative to the actual computation time. The programming model prior to MTAPI, required complex, low-level synchronization and programming with threads, was limited to single operating systems running on single homogeneous multicore processors. 

The MTAPI specification eliminates these obstacles by providing an API allowing programmers to develop parallel embedded software with familiar programming processes. MTAPI features include runtime scheduling and mapping of tasks to processor cores. Optionally, the MTAPI implementation provides access to hardware-implemented actions and/or queues to take advantage of processor-specific features and to increase performance. 
Unlike existing APIs that provide task management functionality (e.g. OpenMP, TBB, Cilk, OpenCL), the MTAPI specification allows implementations for resource-constrained embedded systems, such as those with a small memory footprint, deterministic behavior, and allow for hardware-specific optimizations. Furthermore, portability is essential for the implementation. MTAPI will support different processor architectures and can be implemented in plain C language programing on top of different operating systems or as a bare-metal solution. In short, MTAPI supports asymmetric multiprocessing at the hardware and software level.

Urs Gleim, head of the Parallel Systems research group at Siemens AG, Corporate Technology, in Germany, is chairing the MTAPI Working Group, with technical experts participating from industry and academia including: ENEA, Freescale Semiconductor, Institut National des Sciences Appliquées de Rennes, Qualcomm, Plurality, PolyCore Software, Siemens, Texas Instruments, University of Houston, and Wind River.

“MTAPI greatly simplifies the programming challenge to optimize task management and parallel programming on complex SoCs supporting heterogeneous architectures and hardware acceleration units,” said Urs Gleim. “In addition to its support for portability across multicore processor platforms, MTAPI’s dynamic runtime support will allow the implementer to optimize for quality of service as well as power management that is based on real-time performance demands.”

“MTAPI is aligned with our previously released specifications, Multicore Resource Management API (MRAPI) and the Multicore Communications API (MCAPI). As a matter of fact, MRAPI can be used as part of MTAPI’s internal portability layer, and similarly, the MCAPI may be used for inter-node communications,” said Markus Levy, Multicore Association president. “On a different note, I’d like to thank Mr. Gleim and the members of the working group for their efforts on this project and for recognizing the great value that MTAPI will bring to the industry.”

The MTAPI specification is available for free download from the Multicore Association website. In addition, MCA is providing an MTAPI overview document (called the MTAPI Nutshell) and a detailed reference card. Inquiries regarding membership in the Multicore Association and participation in any working group can be made to Markus Levy (

About The Multicore Association

The Multicore Association provides a neutral forum for vendors who are working with and/or proliferating multicore-related products, including processors, infrastructure, devices, software, and applications. The consortium has made available its Multicore Communications API (MCAPI), Multicore Resource Management API (MRAPI), and Multicore Task Management API (MTAPI) specifications, and its Multicore Programming Practices Guide (MPP) through its website. The consortium also has a working group (TIWG) defining a common data format and creating standards-based mechanisms to share data across diverse and non-interoperable development tools for homogeneous and heterogeneous multicore systems, specifically related to the interfaces between profilers and analysis/visualization tools.

Members include Abo Akademi University, Advanced Cluster Systems, Broadcom, Carnegie Mellon University, Cavium Networks, Codeplay, Delft University of Technology, EADS, Ecole Polytechnique de Montreal, EfficiOS, Enea, Ericsson, eSOL, Freescale Semiconductor, Huawei, Institute of Electronics and Telecommunications of Rennes, LG Electronics, Lockheed Martin, LSI, Mentor Graphics, MIPS Technologies, National Instruments, nCore Design, Netronome, Nokia Siemens Networks, PolyCore Software, Qualcomm, Sage Electronic Engineering, Siemens AG, Tampere University of Technologies, Texas Instruments, Timing Architects, UAS Technikum Wien, University of Houston, and Wind River. Further information is available at

Leave a Reply

featured blogs
May 8, 2024
Learn how artificial intelligence of things (AIoT) applications at the edge rely on TSMC's N12e manufacturing processes and specialized semiconductor IP.The post How Synopsys IP and TSMC’s N12e Process are Driving AIoT appeared first on Chip Design....
May 2, 2024
I'm envisioning what one of these pieces would look like on the wall of my office. It would look awesome!...

featured video

Why Wiwynn Energy-Optimized Data Center IT Solutions Use Cadence Optimality Explorer

Sponsored by Cadence Design Systems

In the AI era, as the signal-data rate increases, the signal integrity challenges in server designs also increase. Wiwynn provides hyperscale data centers with innovative cloud IT infrastructure, bringing the best total cost of ownership (TCO), energy, and energy-itemized IT solutions from the cloud to the edge.

Learn more about how Wiwynn is developing a new methodology for PCB designs with Cadence’s Optimality Intelligent System Explorer and Clarity 3D Solver.

featured paper

Altera® FPGAs and SoCs with FPGA AI Suite and OpenVINO™ Toolkit Drive Embedded/Edge AI/Machine Learning Applications

Sponsored by Intel

Describes the emerging use cases of FPGA-based AI inference in edge and custom AI applications, and software and hardware solutions for edge FPGA AI.

Click here to read more

featured chalk talk

Exploring the Potential of 5G in Both Public and Private Networks – Advantech and Mouser
Sponsored by Mouser Electronics and Advantech
In this episode of Chalk Talk, Amelia Dalton and Andrew Chen from Advantech investigate how we can revolutionize connectivity with 5G in public and private networks. They explore the role that 5G plays in autonomous vehicles, smart traffic systems, and public safety infrastructure and the solutions that Advantech offers in this arena.
Apr 1, 2024