industry news
Subscribe Now

PLS’s Universal Debug Engine (UDE) 4.0.2: Optimized debugging solution for the new ARM® Cortex™-M0 core-based XMC1000 microcontroller family of Infineon

Lauta, January 30, 2013 –  PLS Programmierbare Logik & Systeme presents an optimized test and debugging solution, the Universal Debug Engine (UDE) version 4.0.2, for the new ARM® Cortex™-M0 core-based 32-bit microcontroller family XMC1000 of Infineon Technologies that delivers 32-bit performance at 8-bit prices.

Both the UDE 4.0.2 and PLS’s Universal Access Device family seamlessly support the internal debugging resources and peripheral units of the highly integrated XMC1000 components developed for use in intelligent sensor and actuator applications, LED controls, digital power conversion, and controllers for low-end electric motors, for example. The integrated FLASH/OTP programming functionality of the UDE guarantees maximum speeds in the whole Delete-Download-Programming-Verify cycle.

In order to be able to offer developers as many internal debugging options as possible despite the compact design – the new MCUs are accommodated in TSSOP packages with 16, 28 and 38 pins maximum – Infineon has implemented a series of different boot modes in the microcontrollers. These contain access via a serial bootstrap loader for simple FLASH programming, Serial Wire Debug (SWD) as the standard ARM® Cortex™ processor debugging interface and a single pin debug mode designed by Infineon to yield more I/O pins for the application. The various boot modes are configured automatically by using the UDE 4.0.2 and a universal access device. The devices supplied ex works in serial bootstrap loader mode are thus, for example, reconfigured to SWD mode transparently for the user when connected to the debugger.

The various possibilities for graphically displaying variables and their links to physical values within the Universal Debug Engine benefit above all from the real-time properties of the XMC1000 family. For example, it is possible for the debugger to read and write the entire main memory whilst a program is running without impairing real-time behavior. This permits the animation of variables, registers and memory content at runtime. In addition, the periodic recording of the instruction counter permits a profiling function with portrayal of the percentage share of functions in the application’s runtime.

Dr. Stephan Zizala, Senior Director Industrial and Multimarket Microcontrollers at Infineon Technologies, emphasizes the benefit with the simultaneous availability of the new XMC1000 series and PLS‘s UDE 4.0.2 allowing developers an especially rapid time to market: “PLS’s tools for debugging deeply embedded microcontroller applications are a very good complement to the new Infineon XMC1000 family of low-end 32-bit microcontrollers with their powerful application-optimized peripheral set. Infineon decided on PLS‘s Universal Debug Engine for chip verification as well as for testing the first XMC1000 components. With the UDE 4.0.2, developers have a debugging tool which is fully developed in every respect and available at the XMC1000 market launch in March 2013.”

PLS also sees significant benefits for developers in this approach: “For deeply embedded SoCs, like the microcontroller of the XMC1000 family, it is extremely important for the user to have stable and aligned tools available right from the start. The properties of the powerful ARM® Cortex(tm)-M0 core in combination with Infineon’s optimized peripheral microcontrollers cannot really be used to the full extend without such tools like the Universal Debug Engine”, according to Product Marketing Manager Heiko Riessland. 

The Universal Debug Engine UDE 4.0.2 for the XMC1000 MCU family is available immediately. Further information on the XMC1000 family delivering 32-bit performance at 8-bit prices is available at www.infineon.com/xmc1000 and for the Universal Debug Engine at www.pls-mc.com

PLS Programmierbare Logik & Systeme GmbH

PLS Programierbare Logik & Systeme GmbH, based in Lauta, Germany, was founded in 1990 by Thomas Bauch and Dr. Stefan Weisse. With its innovative modular test and development tools, the company has demonstrated for over two decades its position as an international technology leader in the field of debuggers, emulators and trace solutions for 16-bit and 32-bit microcontrollers. The software architecture of the Universal Debug Engine (UDE) guarantees optimal conditions for debugging SoC-based systems. For example, by means of the intelligent use of modern on-chip debugging and on-chip trace units, valuable functions such as profiling and code coverage are available for the system optimization. Furthermore, the associated Universal Access Device (UAD2/UAD3+) product family, with transfer rates of up to 3.5 MBytes/s and a wide range of interfaces, offers entirely new dimensions for fast and flexible access to multi-core systems. Important architectures such as TriCore, Power Architecture, XC2000/XE166, ARM, Cortex, SH-2A, XScale and C166/ST10 as well as simulation platforms of different vendors are supported. For further information about the company, please visit www.pls mc.com.

Leave a Reply

featured blogs
Apr 26, 2024
LEGO ® is the world's most famous toy brand. The experience of playing with these toys has endured over the years because of the innumerable possibilities they allow us: from simple textbook models to wherever our imagination might take us. We have always been driven by ...
Apr 26, 2024
Biological-inspired developments result in LEDs that are 55% brighter, but 55% brighter than what?...
Apr 25, 2024
See how the UCIe protocol creates multi-die chips by connecting chiplets from different vendors and nodes, and learn about the role of IP and specifications.The post Want to Mix and Match Dies in a Single Package? UCIe Can Get You There appeared first on Chip Design....

featured video

How MediaTek Optimizes SI Design with Cadence Optimality Explorer and Clarity 3D Solver

Sponsored by Cadence Design Systems

In the era of 5G/6G communication, signal integrity (SI) design considerations are important in high-speed interface design. MediaTek’s design process usually relies on human intuition, but with Cadence’s Optimality Intelligent System Explorer and Clarity 3D Solver, they’ve increased design productivity by 75X. The Optimality Explorer’s AI technology not only improves productivity, but also provides helpful insights and answers.

Learn how MediaTek uses Cadence tools in SI design

featured paper

Designing Robust 5G Power Amplifiers for the Real World

Sponsored by Keysight

Simulating 5G power amplifier (PA) designs at the component and system levels with authentic modulation and high-fidelity behavioral models increases predictability, lowers risk, and shrinks schedules. Simulation software enables multi-technology layout and multi-domain analysis, evaluating the impacts of 5G PA design choices while delivering accurate results in a single virtual workspace. This application note delves into how authentic modulation enhances predictability and performance in 5G millimeter-wave systems.

Download now to revolutionize your design process.

featured chalk talk

Electromagnetic Compatibility (EMC) Gasket Design Considerations
Electromagnetic interference can cause a variety of costly issues and can be avoided with a robust EMI shielding solution. In this episode of Chalk Talk, Amelia Dalton chats with Sam Robinson from TE Connectivity about the role that EMC gaskets play in EMI shielding, how compression can affect EMI shielding, and how TE Connectivity can help you solve your EMI shielding needs in your next design.
Aug 30, 2023
29,143 views