industry news
Subscribe Now

ITRI Tapes Out 3D-IC Chip Using Cadence Technology

SAN JOSE, CA–(Marketwire – October 15, 2012) – Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, announced today that its full suite of 3D-IC technologies were deployed by Taiwan’s Industrial Technology Research Institute (ITRI) to develop a 3D-IC chip. Working together, engineers from Cadence® and ITRI used the integrated Cadence 3D-IC flow to implement, analyze, and verify the test chip — a wide I/O memory stack with through-silicon vias (TSVs). The 3D-IC approach — in which multiple ICs are stacked in a single package — is becoming increasingly necessary to meet the size, cost, power, and performance demands for advanced electronics.

“We have been collaborating closely with Cadence for more than a year, using its end-to-end 3D-IC flow to address the challenges in designing with stacked dies and TSVs,” said Dr. Cheng-Wen Wu, general director of Information and Communications Research Laboratories (ICL) and vice president at ITRI. “As a result of the deep collaboration, we now have successfully taped out our first 3D-IC chip. We look forward to continuing our leading work with Cadence in this rapidly emerging area.”Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, announced today that its full suite of 3D-IC technologies were deployed by Taiwan’s Industrial Technology Research Institute (ITRI) to develop a 3D-IC chip. Working together, engineers from Cadence® and ITRI used the integrated Cadence 3D-IC flow to implement, analyze, and verify the test chip — a wide I/O memory stack with through-silicon vias (TSVs). The 3D-IC approach — in which multiple ICs are stacked in a single package — is becoming increasingly necessary to meet the size, cost, power, and performance demands for advanced electronics.

Cadence technologies deployed include Encounter® RTL Compiler, Encounter Digital Implementation System, Encounter Test, Encounter Timing System, Encounter Power System, the Cadence Physical Verification System, and QRC Extraction.

“Cadence is working with advanced customers to address emerging technology challenges like 3D-IC design, offering a uniquely deep set of integrated technologies that span custom/analog, digital, design for test, and package environments,” said Dr. Chi-Ping Hsu, senior vice president, Silicon Realization Group at Cadence. “We recognize the benefits the industry receives from leading research organizations like ITRI that are working to help bring the benefits of 3D-IC design to the semiconductor industry faster.”

About Cadence

Cadence enables global electronic design innovation and plays an essential role in the creation of today’s integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.


Leave a Reply

featured blogs
May 2, 2024
I'm envisioning what one of these pieces would look like on the wall of my office. It would look awesome!...
Apr 30, 2024
Analog IC design engineers need breakthrough technologies & chip design tools to solve modern challenges; learn more from our analog design panel at SNUG 2024.The post Why Analog Design Challenges Need Breakthrough Technologies appeared first on Chip Design....

featured video

MaxLinear Integrates Analog & Digital Design in One Chip with Cadence 3D Solvers

Sponsored by Cadence Design Systems

MaxLinear has the unique capability of integrating analog and digital design on the same chip. Because of this, the team developed some interesting technology in the communication space. In the optical infrastructure domain, they created the first fully integrated 5nm CMOS PAM4 DSP. All their products solve critical communication and high-frequency analysis challenges.

Learn more about how MaxLinear is using Cadence’s Clarity 3D Solver and EMX Planar 3D Solver in their design process.

featured paper

Designing Robust 5G Power Amplifiers for the Real World

Sponsored by Keysight

Simulating 5G power amplifier (PA) designs at the component and system levels with authentic modulation and high-fidelity behavioral models increases predictability, lowers risk, and shrinks schedules. Simulation software enables multi-technology layout and multi-domain analysis, evaluating the impacts of 5G PA design choices while delivering accurate results in a single virtual workspace. This application note delves into how authentic modulation enhances predictability and performance in 5G millimeter-wave systems.

Download now to revolutionize your design process.

featured chalk talk

Exploring the Potential of 5G in Both Public and Private Networks – Advantech and Mouser
Sponsored by Mouser Electronics and Advantech
In this episode of Chalk Talk, Amelia Dalton and Andrew Chen from Advantech investigate how we can revolutionize connectivity with 5G in public and private networks. They explore the role that 5G plays in autonomous vehicles, smart traffic systems, and public safety infrastructure and the solutions that Advantech offers in this arena.
Apr 1, 2024
4,490 views