Leuven (Belgium), Honolulu (Hawaii, USA) – June 14, 2012 – At this week’s VLSI Technology Symposium (Honolulu, Hawaii, USA), imec presents significant improvements in performance and reliability of RRAM cells by process improvements and clever stack-engineering, and imec introduces a new modeling approach increasing the fundamental understanding of RRAM process technology. These achievements pave the way towards scalability and manufacturability of RRAM technology.
RRAM is a promising concept for future non-volatile memories because of its high speed, low energy operation, superior scalability, and compatibility with CMOS technology. Its operation relies on the voltage controlled resistance change of a conductive filament in the dielectric of a Metal/Insulator/Metal (MIM) stack. Resistive RAM (RRAM) systems based on HfO2 have been demonstrated to have excellent scaling capabilities (area <10x10nm) and strong reliability due to efficient voltage-controlled management of oxygen motion in the stack during switching.
At VLSI, imec demonstrates asymmetric bipolar RRAM cells with high-performance and ultra-low operation current (<500nA). This was realized through clever stack engineering leading to novel insights into the switching phenomenology of the cells. An Hf scavenging layer was proven to be key in the stack asymmetry of defect distribution and in the forming process. The state resistances were controlled by introducing Al2O3 as insert layer, HfO2 was kept as a buffer material for further improving the filament resistance control, and stack thinning allowed a lower forming current.
Furthermore, imec presents significant progress in performance and reliability of RRAM cells by process optimizations, which is paving the way for RRAM scaling down to the single digit nm scale. The newly developed patterning of the resistive element (RE), using an optimized house developed etch chemistry, significantly reduced the oxidation at the RE sidewall and increased the performance of the cell. The SiN-last RE encapsulation improved the reliability of the cell (107 cycle of endurance even after 60hrs of bake test at 250C°).
And imec introduces an analytic dynamic hourglass model for Hf2O RRAM. The model describes the set as a constriction growth limited by ion mobility and current compliance, and the reset as a dynamic equilibrium process. The model remains fully analytically tractable and can therefore be implemented in a circuit simulator. The new model captures all main features of the RRAM device operation and reliability, as opposed to former models in which voltage curves were described by a simple dielectric behavior, which was not sufficient to describe low current range behavior of the filaments. Imec’s model increases the fundamental understanding of the filament properties, which is key to bridge the gap in the development of RRAM as a viable next-generation memory technology.
Gosia Jurczak, director of imec’s emerging memory device program: “We are very pleased to present these excellent results. They imply a significant progess in the development of manufacturable process for future RRAM cells. This is why all important memory players worldwide have joined our RRAM research program, because we deliver research that proves value to industry.”
These results were obtained in cooperation with imec’s key partners in its core CMOS programs Globalfoundries, INTEL, Micron, Panasonic, Samsung, TSMC, Elpida, SK hynix, Fujitsu, Toshiba/Sandisk, and Sony.
