Halstenbek, Germany – January 19th, 2012. TEWS TECHNOLOGIES today announced the TAMC651, a standard single Mid-Size or Full-Size AMC.1 module conforming to MTCA.4 (Micro TCA Enhancements for Rear I/O and Precision Timing) with a user-programmable XC6SLX45T-2 or XC6SLX100T-2 Spartan-6 FPGA. Designed for industrial, COTS, and transportation applications, where specialized I/O or long-term availability is required, the TAMC651 provides a number of advantages including a customizable interface for unique applications and a FPGA-based design to extend product lifecycle.
The Spartan-6’s integrated PCIe Endpoint Block is connected to AMC port 4. AMC ports 12-15 (point-to-point) and AMC ports 17-20 (multi-drop) connect to FPGA I/O pins via on-board M-LVDS transceivers.
One of the Spartan-6 GTP transceiver utilizes an SFP interface available at the front plate. SFP support signals are available as FPGA I/O pins. Four FPGA controlled LEDs are also available at the front plate.
According to MTCA.4, the TAMC651 provides two 30-pair ADF connectors at the Zone 3 interface (Rear I/O).
The following I/O signals are available at the Zone 3 interface: 46 differential FPGA I/O lines (LVDS), 2 differential reference clock lines (LVDS), 2 Spartan-6 GTP transceivers. The differential FPGA I/O lines could also be used as single-ended I/O lines (FPGA bank supply for the Zone 3 I/O signals is 2.5V).
The TAMC651 provides a 128 Mbyte, 16 bit wide DDR3 SDRAM bank. The SDRAM-interface uses one of the internal hardwired Memory Controller Blocks of the Spartan-6 FPGA.
The FPGA is configured by a platform Flash. The Flash device is programmable via JTAG header. The JTAG header also supports readback and real-time debugging of the FPGA design (using Xilinx ChipScope).
A programmable clock generator supplies differential clock lines to FPGA global clock pins, to an on-board clock crosspoint-switch and to the Spartan-6 GTP transceiver used for the SFP interface. The clock generator is programmable by the FPGA design.
The TAMC651 also provides a configurable clock crosspoint-switch. Clock inputs are: programmable clock generator output, FPGA clock output, AMC TCLKA and TCLKB. Two clock outputs are connected to FPGA global clock pins and two clock outputs are available as reference clocks at the Zone 3 interface.
User applications can be developed using the design software ISE WebPACK from Xilinx.
The Engineering Documentation TAMC640-ED for FPGA programming includes all information needed for customer specific FPGA programming with additional Constraints Files. The FPGA Development kit TAMC640-FDK includes a basic example design which includes .ucf-files and well documented VHDL example applications. In addition, TEWS offers extensive software driver support for major operating systems such as Windows, LynxOS, Linux, Integrity, VxWorks, and QNX.
About TEWS TECHNOLOGIES
TEWS TECHNOLOGIES is a leading solutions provider of embedded I/O and CPU products based on open architecture standards such as PMC, XMC, IndustryPack® (IP), CompactPCI, standard PCI, AMC, FMC, and VME. TEWS has more than 30 years of experience designing and building turn-key embedded interface solutions using the philosophy to listen and respond to our customers’ needs. Using this ‘customer first’ approach, TEWS has developed a large number of standard and custom products for industrial control, telecommunication infrastructure, medical equipment, traffic control and COTS applications. TEWS’ line of embedded I/O solutions is available worldwide through a global network of distributors. For more information, go to www.tews.com.
