industry news
Subscribe Now

NXP Cortex-M0 Microcontrollers in High-Volume TSSOP and SO Packages Target 8/16-bit Applications

Eindhoven, Netherlands and San Jose, California, October 25, 2011 – NXP Semiconductors N.V. (NASDAQ: NXPI) today announced the availability of new low-pin-count package options – SO20, TSSOP20, TSSOP28 and DIP28 – for its market-leading ARM® Cortex™-M0 LPC1100 family of microcontrollers. The new LPC111x devices are the world’s first 32-bit ARM microcontrollers in low-pin-count packages, and open the door for a broader range of applications previously closed to typical 32-bit MCUs due to package footprint or manufacturing constraints. Target applications include human interface devices (HID), consumer electronics, alarm systems, small appliances and simple motor control, among many others. Starting at $0.49, NXP’s low-pin-count devices deliver 50 MIPS of performance compared to the 1 to 5 MIPS performance typical of 8/16-bit MCUs, at a highly competitive price point enabled by NXP’s exceptional capacity in manufacturing high-volume commodity packages.

“Our Cortex-M0 family has grown to become the most complete offering for entry-level 32-bit MCUs, and today we extend it to an unprecedented $0.01-per-MIPS value for traditional 8/16-bit applications,” said Pierre-Yves Lesaicherre, senior vice president and general manager, microcontrollers and logic, NXP Semiconductors. “Shipping over three billion TSSOP and SO packages per year gives us the flexibility and scale to continuously drive towards lower price points and to introduce sub-40 cent 32-bit MCU solutions in 2012.”

With the world’s smallest 32-bit MCU, the LPC1102, available in a 2-mm x 2-mm Chip-Scale Package (CSP), NXP is at the forefront of innovation in microcontroller packaging and has the widest selection of package options for Cortex-M0 MCUs. The introduction of the new low-pin-count package options provide reduced footprint and system-cost benefit to customers throughout the product development cycle. SO and DIP packages provide ease of customer prototyping with the ability to hand-solder, simplifying hardware requirements for programming and debugging. TSSOP packages eliminate potential reflow process in high-volume production. These easy-to-use and highly reliable packages are popular among 8/16-bit customers and help minimize the number of manufacturing processes while improving yield to further reduce overall system costs. Existing LPC1100 customers can easily convert their designs to the LPC111x low-pin-count devices and reuse their software due to the identical Cortex-M0 instruction set. In addition, these low-pin-count packages are designed for easy PCB layout and scalability by sharing the same pin-out for VDD, VSS, GND, and XTAL.

The LPC1100 series can execute sophisticated algorithms at low power, meeting the ever-increasing demands of cost-sensitive applications that 8-bit microcontrollers struggle to achieve, such as interfacing with sensors and performing complex control tasks. For example, a 16-bit multiply operation performed by an 8-bit microcontroller requires 48 clock cycles at over 770 uA/MHz, while an LPC1100 device can complete the same task in 1 cycle at 130 uA/MHz.

Along with this high performance capability, NXP’s Cortex-M0 LPC1100 family also has numerous innovations in its design:

  • Timers with PWM generation – For each timer, up to four match registers can be configured as PWM, allowing each timer to support up to three match outputs as single edge controlled PWM outputs.
  • Dynamic system clock switching – Change frequency on the fly depending on processing demand. The LPC1100 current consumption at 50 MHz is specified at 7 mA. This can be reduced to a little over 130 uA when running at 1 MHz on the low-power internal oscillator.
  • Clock output – The clock output with divider can reflect the system oscillator clock, IRC clock, CPU clock, and the Watchdog clock. The output can source downstream devices such as other microcontrollers, CPLD or FPGA.
  • Interrupt via any GPIO –Any GPIO pins can be used as Edge- and Level-Sensitive interrupt sources.
  • Programmable pull up/down/open drain – Internal pull-up/pull-down resistor, pseudo open drain or bus keeper function.
  • Enhanced GPIO pin manipulation – Capable of simultaneously reading Bit/Byte/Word or toggling up to 22 I/Os per instruction.

These unique features not only bring design and system benefits, but also help to accelerate the replacement of 8/16-bit MCUs in many applications. Other key specifications for the LPC111x devices include:

  • Cortex-M0 CPU at 130 uA/MHz, up to 50-MHz CPU clock
  • Up to 4 KB SRAM and 32 KB Flash
  • SPI, UART and I2C (Fast-mode Plus)
  • 5-channel 10-bit ADC
  • Two 32-bit Timers and two 16-bit Timers
  • 1% accuracy, 12-MHz IRC
  • Power Profile options via API calls

Tools

All NXP Cortex-M microcontrollers are software compatible and offer all the advantages of a single development toolchain. Users can easily migrate their designs between Cortex-M0 and Cortex-M3 with minimal effort. The easy-to-use LPCXpresso IDE for the LPC1100 series is priced under US $30. For further information on LPCXpresso and other third-party development tools, see www.nxp.com/lpcxpresso, or attend one of the NXP sponsored sessions at ARM TechCon 2011 this week for a free development tool.

Pricing and Availability

Recommended distribution unit pricing for 10,000 piece quantities is US $0.49 for the LPC1110FD20. Samples are available in November 2011. Additional information is available at http://www.nxp.com/products/microcontrollers/cortex_m0/lpc1100l/

Links

About NXP Semiconductors

NXP Semiconductors N.V. (NASDAQ: NXPI) provides High Performance Mixed Signal and Standard Product solutions that leverage its leading RF, Analog, Power Management, Interface, Security and Digital Processing expertise. These innovations are used in a wide range of automotive, identification, wireless infrastructure, lighting, industrial, mobile, consumer and computing applications. A global semiconductor company with operations in more than 25 countries, NXP posted revenue of $4.4 billion in 2010. Additional information can be found by visiting www.nxp.com.

Leave a Reply

featured blogs
Apr 13, 2021
We explain the NHTSA's latest automotive cybersecurity best practices, including guidelines to protect automotive ECUs and connected vehicle technologies. The post NHTSA Shares Best Practices for Improving Autmotive Cybersecurity appeared first on From Silicon To Software....
Apr 13, 2021
If a picture is worth a thousand words, a video tells you the entire story. Cadence's subsystem SoC silicon for PCI Express (PCIe) 5.0 demo video shows you how we put together the latest... [[ Click on the title to access the full blog on the Cadence Community site. ]]...
Apr 12, 2021
The Semiconductor Ecosystem- It is the definition of '€œHigh Tech'€, but it isn'€™t just about… The post Calibre and the Semiconductor Ecosystem appeared first on Design with Calibre....
Apr 8, 2021
We all know the widespread havoc that Covid-19 wreaked in 2020. While the electronics industry in general, and connectors in particular, took an initial hit, the industry rebounded in the second half of 2020 and is rolling into 2021. Travel came to an almost stand-still in 20...

featured video

The Verification World We Know is About to be Revolutionized

Sponsored by Cadence Design Systems

Designs and software are growing in complexity. With verification, you need the right tool at the right time. Cadence® Palladium® Z2 emulation and Protium™ X2 prototyping dynamic duo address challenges of advanced applications from mobile to consumer and hyperscale computing. With a seamlessly integrated flow, unified debug, common interfaces, and testbench content across the systems, the dynamic duo offers rapid design migration and testing from emulation to prototyping. See them in action.

Click here for more information

featured paper

From Chips to Ships, Solve Them All With HFSS

Sponsored by Ansys

There are virtually no limits to the design challenges that can be solved with Ansys HFSS and the new HFSS Mesh Fusion technology! Check out this blog to know what the latest innovation in HFSS 2021 can do for you.

Click here to read the blog post

Featured Chalk Talk

TensorFlow to RTL with High-Level Synthesis

Sponsored by Cadence Design Systems

Bridging the gap from the AI and data science world to the RTL and hardware design world can be challenging. High-level synthesis (HLS) can provide a mechanism to get from AI frameworks like TensorFlow into synthesizable RTL, enabling the development of high-performance inference architectures. In this episode of Chalk Talk, Amelia Dalton chats with Dave Apte of Cadence Design Systems about doing AI design with HLS.

More information