industry news
Subscribe Now

Mentor Graphics and GLOBALFOUNDRIES Improve Yield Analysis with Combination of Tessent and Calibre Capabilities

WILSONVILLE, Ore., August 29, 2011 – Mentor Graphics Corporation (NASDAQ: MENT) today announced an innovative approach to IC yield analysis that combines the layout-aware production test failure diagnosis capabilities of the Tessent® Diagnosis and Tessent YieldInsight® products with the design for manufacturing (DFM) analysis facilities of the Calibre® YieldAnalyzer tool. The new methodology enables customers to identify and understand systematic yield loss, and to determine if the systematic yield loss is correlated to DFM violations.

“Diagnosis-driven yield analysis is an established yield-learning methodology at GLOBALFOUNDRIES for internal technology development, as well as for accelerating the yield ramp for our customer products,” said Thomas Herrmann, MTS product engineer, GLOBALFOUNDRIES. “The addition of DFM-aware yield analysis helps us and our customers to separate design-and process-related yield limiters, and reduces the time to find the root causes of yield loss. We can also use the technology to optimize DFM rules to address specific customer needs and priorities, which leads to reduced manufacturing variability for re-spins and future designs.”

In the DFM-aware yield analysis flow, test data from digital semiconductor devices that have failed manufacturing test is used to perform layout-aware failure diagnosis with the Tessent Diagnosis product, which provides information such as defect classifications and suspected defect locations. The Calibre YieldAnalyzer product leverages GLOBALFOUNDRIES’ Manufacturing Analysis and Scoring (MAS) deck to identify features of the layout that have higher sensitivities to manufacturing variability. The Tessent YieldInsight product analyzes this information to identify and understand systematic yield loss, and determine if this yield loss is associated with known DFM-sensitive layout structures.

“Mentor continues to drive towards meaningful interactions between the design and manufacturing test flows,” said Greg Aldrich, marketing director for the Silicon Test Solutions group at Mentor Graphics. “This is much more than allowing tools to exchange data—it’s incorporating powerful data mining and statistical analysis capabilities that leverage the knowledge and experience of experts from both the design and manufacturing areas.”

About Mentor Graphics

Mentor Graphics Corporation (NASDAQ: MENT) is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world’s most successful electronic, semiconductor and systems companies. Established in 1981, the company reported revenues over the last 12 months of about $915 million. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777. World Wide Web site: http://www.mentor.com/

Leave a Reply

featured blogs
Nov 25, 2020
It constantly amazes me how there are always multiple ways of doing things. The problem is that sometimes it'€™s hard to decide which option is best....
Nov 25, 2020
[From the last episode: We looked at what it takes to generate data that can be used to train machine-learning .] We take a break from learning how IoT technology works for one of our occasional posts on how IoT technology is used. In this case, we look at trucking fleet mana...
Nov 25, 2020
It might seem simple, but database units and accuracy directly relate to the artwork generated, and it is possible to misunderstand the artwork format as it relates to the board setup. Thirty years... [[ Click on the title to access the full blog on the Cadence Community sit...
Nov 23, 2020
Readers of the Samtec blog know we are always talking about next-gen speed. Current channels rates are running at 56 Gbps PAM4. However, system designers are starting to look at 112 Gbps PAM4 data rates. Intuition would say that bleeding edge data rates like 112 Gbps PAM4 onl...

featured video

Introduction to the fundamental technologies of power density

Sponsored by Texas Instruments

The need for power density is clear, but what are the critical components that enable higher power density? In this overview video, we will provide a deeper understanding of the fundamental principles of high-power-density designs, and demonstrate how partnering with TI, and our advanced technological capabilities can help improve your efforts to achieve those high-power-density figures.

featured paper

Overcoming PPA and Productivity Challenges of New Age ICs with Mixed Placement Innovation

Sponsored by Cadence Design Systems

With the increase in the number of on-chip storage elements, it has become extremely time consuming to come up with an optimized floorplan using manual methods, directly impacting tapeout schedules and power, performance, and area (PPA). In this white paper, learn how a breakthrough technology addresses design productivity along with design quality improvements for macro-dominated designs. Download white paper.

Click here to download the whitepaper

featured chalk talk

UWB: Because Location Matters

Sponsored by Mouser Electronics and Qorvo

While technologies like GPS, WiFi, and Bluetooth all offer various types of location services, none of them are well-suited to providing accurate, indoor/outdoor, low-power, real-time, 3D location data for edge and endpoint devices. In this episode of Chalk Talk, Amelia Dalton chats with Mickael Viot from Qorvo about ultra-wideband (UWB) technology, and how it can revolutionize a wide range of applications.

Click here for more information about Qorvo Ultra-Wideband (UWB) Technology