industry news
Subscribe Now

Calypto Design Systems Acquires Mentor Catapult C Synthesis Tool

SANTA CLARA, Calif. August 26, 2011 – Calypto Design Systems today announced it has acquired Catapult C Synthesis from Mentor Graphics Corporation (NASDAQ: MENT). The merger of two market-leading electronic system level (ESL) products, Catapult C Synthesis and Calypto SLEC System-HLS verification tool, will create a better integrated ESL hardware realization flow, and enhance the company’s partnership with Mentor Graphics, a leader in ESL technology. Terms of the transaction were not disclosed. 

”ESL synthesis offers our design community the next great leap in productivity. Much like the move to RTL years ago, the move to higher levels of abstraction based on C and SystemC offers the promise of better quality of results in a shorter amount of time. By combining the market leading products in C synthesis, sequential verification, and power optimizationwithin Calypto, we will be the only company capable of delivering a fully integrated flow, and delivering on that promise of ESL,” said Doug Aitelli, Chief Executive Officer of Calypto Design Systems. “In addition, we remain fully committed to our existing high level synthesis partnerships and to industry-wide interoperability.”

“This is a great deal for Calypto,” said Gary Smith, Chief Analyst at GSEDA. “They are clearly one of the companies on the rise in ESL, and this gives them the chance to offer a compelling power-optimized C to RTL flow if they can integrate all the pieces.”

ESL methods allow designers to work at a higher level of abstraction, greatly reducing errors and allowing greater optimization of integrated circuits (IC) in key attributes like speed and power. To adopt ESL methods, designers need to have confidence that tools, as they translate from the higher level of abstraction to lower levels, don’t introduce errors. Typically, designers have used extensive RTL verification to ensure that no errors have been introduced.

SLEC System-HLS uniquely addresses this challenge with C to RTL formal equivalence checking using patented sequential analysis technology to create an easy to use synthesis and verification flow environment. Designers can perform comprehensive functional verification using SLEC System?HLS to formally verify equivalence between SystemC ESL models and RTL implementations. This leads to up to 100x speed up times in RTL verification as it removes the need for significant and time consuming RTL simulation to validate that the RTL matches the C or SystemC source. Tight integration between Calypto’s SLEC System-HLS and Catapult C Synthesis will give designers confidence that the IC they designed in C or SystemC is the IC that is being delivered in RTL.

Additionally, the PowerPro SoC Power Reduction Platform can do RTL level power optimizations. Added to the Catapult C Synthesis and SLEC System-HLS hardware realization flow, this allows designers to swiftly go from C and System C designs to power-optimized RTL.

“We remain deeply committed to ESL. We view this transaction as an innovative way to accelerate adoption of ESL methodologies, to strengthen our partnership with Calypto, and as one that complements our continued investment in ESL virtual prototyping environments led by our Vista product,” said Brian Derrick, vice president of marketing at Mentor Graphics. “Calypto’s Sequential Logic Equivalency Checker is a critical and unique technology for enabling the adoption of ESL. Its combination with the market-leading Catapult C Synthesis product and the PowerPro SoC Power Reduction Platform, should give designers the confidence to adopt ESL methods and enjoy the significant benefits that designing at higher levels of abstraction brings.”

Current customers of the Mentor Graphics Catapult C Synthesis tool will continue to be supported by Mentor Graphics. Moving forward, any new customer sales and support will be supplied by Calypto.

About Calypto Design Systems

Calypto Design Systems, Inc. empowers designers to create high?quality, low-power electronic systems by providing best?in?class power optimization and functional verification software, based on its patented Sequential Analysis Technology. Calypto, whose customers include Fortune 500 companies worldwide, is a member of the Cadence Connections program, the IEEE?SA, Synopsys SystemVerilog Catalyst Program, the Mentor Graphics OpenDoor program, Si2, ARM Connected Community and is an active participant in the Power Forward Initiative. Calypto has offices in Europe, India, Japan and North America. More information can be found at: www.calypto.com.

Leave a Reply

featured blogs
Jun 30, 2022
The Team RF "μWaveRiders" blog series is a showcase for Cadence AWR RF products. Monthly topics will vary between Cadence AWR Design Environment release highlights, feature videos, Cadence... ...
Jun 29, 2022
The 2022 YWCA Golden Gate Silicon Valley Tribute to Women Awards honored five women from the Synopsys team; learn about the award and this year's honorees. The post YWCA Tribute to Women Honors Synopsys Women of Achievement appeared first on From Silicon To Software....
Jun 28, 2022
Watching this video caused me to wander off into the weeds looking at a weird and wonderful collection of wheeled implementations....

featured video

Demo: Achronix Speedster7t 2D NoC vs. Traditional FPGA Routing

Sponsored by Achronix

This demonstration compares an FPGA design utilizing Achronix Speedster7t 2D Network on Chip (NoC) for routing signals with the FPGA device, versus using traditional FPGA routing. The 2D NoC provides a 40% reduction in logic resources required with 40% less compile time needed versus using traditional FPGA routing. Speedster7t FPGAs are optimized for high-bandwidth workloads and eliminate the performance bottlenecks associated with traditional FPGAs.

Subscribe to Achronix's YouTube channel for the latest videos on how to accelerate your data using FPGAs and eFPGA IP

featured paper

Addressing high-voltage design challenges with reliable and affordable isolation tech

Sponsored by Texas Instruments

Check out TI’s new white paper for an overview of galvanic isolation techniques, as well as how to improve isolated designs in electric vehicles, grid infrastructure, factory automation and motor drives.

Click to read more

Featured Chalk Talk

Direct Drive: Getting More Juice from Your JFET

Sponsored by Mouser Electronics and UnitedSiC

In this episode of Chalk Talk, Jonathan Dodge from UnitedSiC (now part of Qorvo) and Amelia Dalton discuss how you can take full advantage of silicon carbide JFET transistors. They delve into the details of these innovative transistors including what their capacitances look like, how you can control their speed and how you can combine the benefits of a cascode and a directly driven JFET in your next design.

Click here for more information about UnitedSiC UF4C/SC 1200V Gen 4 SiC FETs