industry news
Subscribe Now

Altera Delivers Industry’s First Interface Targeting MoSys’s Serial, High-Density Bandwidth Engine Device

San Jose, Calif., February 8, 2011—Altera Corporation (Nasdaq: ALTR) today announced it successfully completed interoperability testing between its Stratix® IV GT FPGA and the Bandwidth Engine® device from MoSys in a serial memory application. Stratix IV GT FPGAs leverage the GigaChip™ Interface to interoperate with MoSys’s Bandwidth Engine device, providing designers of 100G wireline applications, such as traffic management and packet processing, a high-performance, high-bandwidth memory solution. With its Stratix IV GT FPGA, Altera is the first FPGA vendor to deliver device support for the GigaChip Interface.

Altera is a founding member of the MoSys GigaChip Alliance, which includes semiconductor companies collaborating to enable highly efficient serial chip-to-chip communications in next-generation, high-performance networking, computing and storage systems. The GigaChip Interface leverages transceiver technology to deliver breakthrough chip-to-chip communications performance. MoSys utilized the Stratix IV GT FPGA in the development of the GigaChip Interface as a result of the timely availability of Altera’s high-performance transceiver technology.

“The GigaChip Interface represents a bandwidth density performance increase of 4X over DDR-type interfaces, while reducing system power and interface costs by 2X to 3X,‎ said David DeMaria, vice president of business operations at MoSys. “Our goal is to make it an open industry standard to enable highly efficient chip-to-chip communications, and we are pleased to announce the industry’s first interoperability with Altera. The transceiver technology featured in Stratix IV GT FPGAs provides MoSys an ideal platform for implementing the Bandwidth Engine interface and controller. Altera’s proven transceiver technology combined with its Stratix IV GT FPGAs enables us to deliver to customers today a high-performance serial memory solution targeting next-generation networking systems.”

The GigaChip Interface is a short-reach, low-power serial interface, which enables highly efficient, high-bandwidth, low-latency performance. Stratix IV GT FPGAs support the GigaChip Interface through the device’s soft memory controller, which provide maximum design flexibility, and the device’s 11.3 Gbps transceivers. Supporting the GigaChip Interface within Stratix IV GT FPGAs enables customers to increase system performance, while minimizing board costs and pin counts.

“Incorporating the GigaChip Interface puts Altera in an exceptional position to address the market’s transition to 100G and beyond,” said Luanne Schirrmeister, senior director of component product marketing at Altera. “This interoperability demonstrates to wireline customers that we’re committed to delivering the highest performance solutions in the market.”


Stratix IV GT FPGAs are currently shipping in volume production. Contact your Altera® sales representative for pricing. Additional information regarding Stratix IV FPGAs can be found at MoSys’s Bandwidth Engine devices are sampling now. Additional information regarding the Bandwidth Engine and the GigaChip Interface can be found at

About Altera

Altera® programmable solutions enable system and semiconductor companies to rapidly and cost-effectively innovate, differentiate and win in their markets. Find out more about Altera’s FPGACPLD and ASIC devices at Follow Altera via FacebookRSS and Twitter.

Leave a Reply

featured blogs
Dec 8, 2023
Read the technical brief to learn about Mixed-Order Mesh Curving using Cadence Fidelity Pointwise. When performing numerical simulations on complex systems, discretization schemes are necessary for the governing equations and geometry. In computational fluid dynamics (CFD) si...
Dec 7, 2023
Explore the different memory technologies at the heart of AI SoC memory architecture and learn about the advantages of SRAM, ReRAM, MRAM, and beyond.The post The Importance of Memory Architecture for AI SoCs appeared first on Chip Design....
Nov 6, 2023
Suffice it to say that everyone and everything in these images was shot in-camera underwater, and that the results truly are haunting....

featured video

Dramatically Improve PPA and Productivity with Generative AI

Sponsored by Cadence Design Systems

Discover how you can quickly optimize flows for many blocks concurrently and use that knowledge for your next design. The Cadence Cerebrus Intelligent Chip Explorer is a revolutionary, AI-driven, automated approach to chip design flow optimization. Block engineers specify the design goals, and generative AI features within Cadence Cerebrus Explorer will intelligently optimize the design to meet the power, performance, and area (PPA) goals in a completely automated way.

Click here for more information

featured paper

Power and Performance Analysis of FIR Filters and FFTs on Intel Agilex® 7 FPGAs

Sponsored by Intel

Learn about the Future of Intel Programmable Solutions Group at The power and performance efficiency of digital signal processing (DSP) workloads play a significant role in the evolution of modern-day technology. Compare benchmarks of finite impulse response (FIR) filters and fast Fourier transform (FFT) designs on Intel Agilex® 7 FPGAs to publicly available results from AMD’s Versal* FPGAs and artificial intelligence engines.

Read more

featured chalk talk

Analog in a Digital World: TRIMPOT® Trimming Potentiometers
Sponsored by Mouser Electronics and Bourns
Trimmer potentiometers are a great way to fine tune the output of an analog circuit and can be found used in a wide variety of applications. In this episode of Chalk Talk, Patricia Moorman from Bourns and Amelia Dalton break down the what, where, how, and why of trimpots and the benefits that Bourns trimpots can bring to your next design.
Feb 2, 2023