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Synopsys Galaxy Implementation Platform enables first-pass silicon success on Infineon’s 40-nanometer X-GOLD 626 wireless product

MOUNTAIN VIEW, Calif., March 30, 2010 – Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced that the Galaxy™ Implementation Platform has helped Infineon Technologies AG (NYSE: IFX) achieve first-pass silicon success of the 40-nanometer (nm) baseband processor for its X-GOLD™ 626 3G wireless analogue and digital system-in-package (SIP). Infineon utilised the Galaxy platform’s powerful implementation flow to optimise the chip’s multiple functional modes with multi-corner/multi-mode (MCMM) technology, taking advantage of the links between Synopsys’ Design Compiler® RTL synthesis solution and IC Compiler placement and routing. The Galaxy platform’s extensive support for low power and hierarchical design techniques, coupled with its signoff capabilities, was essential to achieve Infineon’s tight schedule and high-performance, low power and area goals. As a result, Infineon met its design targets and taped out the baseband processor for the X-GOLD 626 wireless product ahead of schedule.

“One of the key challenges we had in designing the X-GOLD 626 baseband processor was optimising the design for highest performance and lowest power, without compromising on robustness and quality,” said Hartmut Hiller, vice president of Design Methodology and Implementation at Infineon Technologies. “Synopsys’ Galaxy platform includes essential advanced low power capabilities which, along with its strength in hierarchical design and concurrent MCMM optimisation, were critical to our first-pass silicon success. Synopsys’ excellent global support and the Galaxy platform’s robust implementation and signoff technologies, we successfully taped out the chip ahead of schedule.”

Infineon’s X-GOLD 626 is a complex multi-million-gate analogue and digital SIP that integrates a power management unit to enable best-in-class power consumption in both active and idle modes. Infineon’s design team captured the chip’s complex power architecture with the IEEE 1801 (UPF) standard. Power management features implemented using the Galaxy platform included voltage islands with MTCMOS power gating and multi-threshold libraries. In addition, by implementing a hierarchical design flow and support for multiple internal clocks, the Galaxy platform delivered outstanding quality of results, meeting Infineon’s high-performance, low power and area goals.

“Our customers are facing several challenges: to produce the highest-quality products within the shortest amount of time and with best-in-class performance, power and area,” said Dr. Antun Domic, senior vice president and general manager, Implementation Group at Synopsys. “Infineon’s decision to deploy our Galaxy Implementation Platform, including IC Compiler, for their advanced wireless designs will enable them to continue to aggressively focus on bringing differentiated wireless SoC solutions to market.”

About Synopsys

Synopsys, Inc. (Nasdaq: SNPS) is a world leader in electronic design automation (EDA), supplying the global electronics market with the software, intellectual property (IP) and services used in semiconductor design, verification and manufacturing. Synopsys’ comprehensive, integrated portfolio of implementation, verification, IP, manufacturing and field-programmable gate array (FPGA) solutions helps address the key challenges designers and manufacturers face today, such as power and yield management, software-to-silicon verification and time-to-results. These technology-leading solutions help give Synopsys customers a competitive edge in bringing the best products to market quickly while reducing costs and schedule risk. Synopsys is headquartered in Mountain View, California, and has more than 65 offices located throughout North America, Europe, Japan, Asia and India. Visit Synopsys online at

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