Researchers at MIT have refined a software-based chip simulator that tests chip designs with large numbers of cores for flaws, adding the ability to measure designs’ potential power consumption, as well as processing times for tasks, memory access, and core-to-core communications patterns. The team from MIT’s Department of Electrical Engineering and Computer Science is using the simulator to test possible designs for a new processor targeted for fabrication later this year—one that they hope will have over 100 cores.
The simulator is called Hornet, Srini Devadas, professor of electrical engineering and computer science at MIT and principle investigator on Hornet, told Ars Technica in an interview. “You can use it to come up with an interesting computer architecture and test it.” When flaws are found, Hornet allows designers to quickly try alternative designs to work around them.
via Wired
March 2, 2012
