fish fry
Subscribe Now

Design Automation for Fun and Profit (But Mostly Fun)

RTL Verification, eFPGAs, and Advanced IC Packaging at DAC 2017

If you have attended the Design Automation Conference in the last couple years, you will know that the scope of this event reaches far beyond your standard EDA tools of years past. Sure, we’re still talking about design automation software, but now there’s a whole slew of IP vendors (and their software compatriots), IC packaging companies, embedded FPGA fabric distributors, and more. This week’s episode of Fish Fry is going to be no different. We’re doing a little soup to nuts –  DAC style.  First, we discuss RTL verification with John Molyneux (President of Blue Pearl Software). Next, we get into embedding FPGA fabric as IP with Owen Bateman (Quicklogic). Lastly, we talk about the newest advancements in IC packaging with John Park (Cadence Design Systems).

 

Download this episode (right click and save)

Links for June 23, 2017

More information about the 2017 Design Automation Conference

More information about Blue Pearl Software

More information about QuickLogic

More information about the Virtuoso System Design Platform from Cadence Design Systems

Click here to check out the Fish Fry Archive.

Click here to subscribe to Fish Fry via Podbean

Click here to get the Fish Fry RSS Feed

Click here to subscribe to Fish Fry via iTunes.

————————————

Fish Fry Executive Interviews

Moshe Gavrielov, CEO – Xilinx

Darrin Billerbeck, CEO – Lattice Semiconductor

Bill Neifert, CTO – Carbon Design Systems

Sean Dart, CEO – Forte Design Systems

Paul Kocher, President – Cryptography Research Inc.

Anupam Bakshi, CEO – Agnisys

Dave Kleidermacher, CTO – Green Hills Software

Robert Blake, CEO – Achronix

Jack Harding, CEO – eSilicon

Michiel Ligthart, COO – Verific

Adnan Hamid, CEO – Breker Technologies

Jeff Waters, VP and General Manager – Altera

Simon Davidmann, CEO – Imperas

Ted Miracco, CEO – SmartFlow Compliance Solutions

Cees Links – GreenPeak Technologies

Jessica Gomez – Rogue Valley Microdevices

Shishpal Rawat, Chairman – Accellera Systems Initiative

Kevin Bromber, CEO – myDevices

Daniel Hansson, CEO – Verifyter

Mark Papermaster, CTO – AMD

David Fried, CTO – Coventor

Dr. Steven LeBoeuf, President – Valencell

David Dutton, CEO – Silvaco

Bob Niemiec, CEO – TwistThink

Allan Martinson, COO – Starship Technologies

Zhihong Liu, Chairman and CEO – ProPlus Solutions

Taher Madraswala, CEO and President – Open-Silicon

Kapil Shankar, CEO and Director – AnDAPT

Mike Wishart, CEO – efabless 

Dan Fox, CTO – Local Motors

Leave a Reply

featured blogs
Apr 12, 2024
Like any software application or electronic gadget, software updates are crucial for Cadence OrCAD X and Allegro X applications as well. These software updates, often referred to as hotfixes, include support for new features and critical bug fixes made available to the users ...
Apr 11, 2024
See how Achronix used our physical verification tools to accelerate the SoC design and verification flow, boosting chip design productivity w/ cloud-based EDA.The post Achronix Achieves 5X Faster Physical Verification for Full SoC Within Budget with Synopsys Cloud appeared ...
Mar 30, 2024
Join me on a brief stream-of-consciousness tour to see what it's like to live inside (what I laughingly call) my mind...

featured video

How MediaTek Optimizes SI Design with Cadence Optimality Explorer and Clarity 3D Solver

Sponsored by Cadence Design Systems

In the era of 5G/6G communication, signal integrity (SI) design considerations are important in high-speed interface design. MediaTek’s design process usually relies on human intuition, but with Cadence’s Optimality Intelligent System Explorer and Clarity 3D Solver, they’ve increased design productivity by 75X. The Optimality Explorer’s AI technology not only improves productivity, but also provides helpful insights and answers.

Learn how MediaTek uses Cadence tools in SI design

featured chalk talk

Package Evolution for MOSFETs and Diodes
Sponsored by Mouser Electronics and Vishay
A limiting factor for both MOSFETs and diodes is power dissipation per unit area and your choice of packaging can make a big difference in power dissipation. In this episode of Chalk Talk, Amelia Dalton and Brian Zachrel from Vishay investigate how package evolution has led to new advancements in diodes and MOSFETs including minimizing package resistance, increasing power density, and more! They also explore the benefits of using Vishay’s small and efficient PowerPAK® and eSMP® packages and the migration path you will need to keep in mind when using these solutions in your next design.
Jul 10, 2023
31,228 views