fish fry
Subscribe Now

It’s All in the Sequence

How is Your Register Behaving?

Registers: It’s a dirty job but someone has to do it. In this week’s Fish Fry, we take a closer look at register behavior modification and sequence automation with Anupam Bakshi of Agnisys. Anupam and I also discuss design intent and the future of verification intent. Whether we like it or not, we all need a little help sometimes, right? In the second part of our EDA special, we welcome Bob Smith from the Electronic System Design Alliance. Bob and I discuss how the ESDA is helping facilitate IP fingerprinting and 3D system scaling, as well as bridging the gap between hardware and software in embedded system design.  

 

 

Download this episode (right click and save)

Links for August 19, 2016

More information about Agnisys

More information about the Electronic System Design Alliance

New Episode of Chalk Talk: Addressing the Challenges of Serial Link Design and Analysis

Fish Fry Executive Interviews

Moshe Gavrielov, CEO – Xilinx

Darrin Billerbeck, CEO – Lattice Semiconductor

Bill Neifert, CTO – Carbon Design Systems

Sean Dart, CEO – Forte Design Systems

Andy Pease, CEO – QuickLogic

Paul Kocher, President – Cryptography Research Inc.

Anupam Bakshi, CEO – Agnisys

Dave Kleidermacher, CTO – Green Hills Software

Robert Blake, CEO – Achronix

Jack Harding, CEO – eSilicon

Michiel Ligthart, COO – Verific

Adnan Hamid, CEO – Breker Technologies

Jeff Waters, VP and General Manager – Altera

Simon Davidmann, CEO – Imperas

Ted Miracco, CEO – SmartFlow Compliance Solutions

Cees Links – GreenPeak Technologies

Jessica Gomez – Rogue Valley Microdevices

Shishpal Rawat, Chairman – Accellera Systems Initiative

Kevin Bromber, CEO – myDevices

Daniel Hansson, CEO – Verifyter

Mark Papermaster, CTO – AMD

David Fried, CTO – Coventor

Dr. Steven LeBoeuf, President – Valencell

David Dutton, CEO – Silvaco



Leave a Reply

featured blogs
May 8, 2024
Learn how artificial intelligence of things (AIoT) applications at the edge rely on TSMC's N12e manufacturing processes and specialized semiconductor IP.The post How Synopsys IP and TSMC’s N12e Process are Driving AIoT appeared first on Chip Design....
May 2, 2024
I'm envisioning what one of these pieces would look like on the wall of my office. It would look awesome!...

featured video

Introducing Altera® Agilex 5 FPGAs and SoCs

Sponsored by Intel

Learn about the Altera Agilex 5 FPGA Family for tomorrow’s edge intelligent applications.

To learn more about Agilex 5 visit: Agilex™ 5 FPGA and SoC FPGA Product Overview

featured paper

Altera® FPGAs and SoCs with FPGA AI Suite and OpenVINO™ Toolkit Drive Embedded/Edge AI/Machine Learning Applications

Sponsored by Intel

Describes the emerging use cases of FPGA-based AI inference in edge and custom AI applications, and software and hardware solutions for edge FPGA AI.

Click here to read more

featured chalk talk

TE Connectivity MULTIGIG RT Connectors
In this episode of Chalk Talk, Amelia Dalton and Ryan Hill from TE Connectivity explore the benefits of TE’s Multigig RT Connectors and how these connectors can help empower the next generation of military and aerospace designs. They examine the components included in these solutions and how the modular design of these connectors make them a great fit for your next military and aerospace design.
Mar 19, 2024
8,466 views