fish fry
Subscribe Now

Hello Rubber, Meet Road

Valencell’s Biometric Testing Takes IoT Out for a Spin

This here twin-turbo EEJournal.com podcastin’ hot rod is headed to the IoT finish line – one biometric at a time. In this week’s Fish Fry, we investigate biometric data sensors and how one company is making sure that our fitness is actually what we think it is. My guest is Valencell President Steven LeBoeuf. Steven and I are going to chat about the future of the wearable market, precision biometrics, Valencell’s new state-of-the-art sports testing lab, and a little bit about professional cartooning. Get your wearable motor runnin’ folks!


 

Download this episode (right click and save)

Links for October 17, 2014

More information about Valencell

Valencell Opens New State of the Art Sports Testing Lab to Support the Development and Validation of Highly Accurate, Precise Biometric Wearables

New Episode of Chalk Talk: 4-Channel Analog Front End Solution

Click Here to take a free survey and enter for a chance to win a MAXSANTAFEEVSYS Kit courtesy of Maxim Integrated.

Leave a Reply

featured blogs
Dec 1, 2023
Why is Design for Testability (DFT) crucial for VLSI (Very Large Scale Integration) design? Keeping testability in mind when developing a chip makes it simpler to find structural flaws in the chip and make necessary design corrections before the product is shipped to users. T...
Nov 27, 2023
See how we're harnessing generative AI throughout our suite of EDA tools with Synopsys.AI Copilot, the world's first GenAI capability for chip design.The post Meet Synopsys.ai Copilot, Industry's First GenAI Capability for Chip Design appeared first on Chip Design....
Nov 6, 2023
Suffice it to say that everyone and everything in these images was shot in-camera underwater, and that the results truly are haunting....

featured video

Dramatically Improve PPA and Productivity with Generative AI

Sponsored by Cadence Design Systems

Discover how you can quickly optimize flows for many blocks concurrently and use that knowledge for your next design. The Cadence Cerebrus Intelligent Chip Explorer is a revolutionary, AI-driven, automated approach to chip design flow optimization. Block engineers specify the design goals, and generative AI features within Cadence Cerebrus Explorer will intelligently optimize the design to meet the power, performance, and area (PPA) goals in a completely automated way.

Click here for more information

featured paper

Power and Performance Analysis of FIR Filters and FFTs on Intel Agilex® 7 FPGAs

Sponsored by Intel

Learn about the Future of Intel Programmable Solutions Group at intel.com/leap. The power and performance efficiency of digital signal processing (DSP) workloads play a significant role in the evolution of modern-day technology. Compare benchmarks of finite impulse response (FIR) filters and fast Fourier transform (FFT) designs on Intel Agilex® 7 FPGAs to publicly available results from AMD’s Versal* FPGAs and artificial intelligence engines.

Read more

featured chalk talk

Electrical Connectors for Hermetically Sealed Applications
Many hermetic chambers today require electrical pathways to provide internal equipment with power, data or signals, or to receive data and signals from equipment within the chamber. In this episode of Chalk Talk, Amelia Dalton and Brad Taras from Cinch Connectivity Solutions explore the role that seals and connectors play in the performance of hermetic chambers. They examine the methodologies to determine hermetic seal leaks, the benefits of epoxy hermetic seals, and how Cinch Connectivity’s epoxy-based seals and hermetic connectors can add value to your next design.
Aug 22, 2023
12,407 views