EEJournal

fish fry
Subscribe Now
July 11, 2014

X Marks the Spot

Thwarting Pirates with AI and X-fest 2014
by Amelia Dalton

At Attention Ye Salty Dogs! Hoist the mizzen mast, Fish Fry is ready to set sail! This week Jim Beneke comes aboard our mighty Fish Fryin’ ship to plot a course to X-Fest – the yearly how-to training sessions from Avnet and Xilinx for FPGA, DSP, SoC and embedded systems designers. Join us as we dig into X-Fest’s treasure trove of deep tech seminars, trainings, and much more. Then, in keeping with our pirateous parade, we delve into the details of a new pirate-busting radarrrr called WatchStander, and check out how artificial intelligence plays an important role in WatchStander’s modus operandi.

 

 

Download this episode (right click and save)

Links for July 11, 2014

Register for X-Fest

More information about X-Fest

More information about WatchStander

Leave a Reply

featured blogs
NASA Turbulence Modeling Symposium 2022 - Roadblocks, and the Potential for Machine Learning
May 20, 2022
This year's NASA Turbulence Modeling Symposium is being held in honor of Philippe Spalart and his contributions to the turbulence modeling field. The symposium will bring together both academic and... ...
More from Cadence...
Key Highlights from SNUG 2022: AI Is Fast Forwarding Chip Design
May 19, 2022
Learn about the AI chip design breakthroughs and case studies discussed at SNUG Silicon Valley 2022, including autonomous PPA optimization using DSO.ai. The post Key Highlights from SNUG 2022: AI Is Fast Forwarding Chip Design appeared first on From Silicon To Software....
More from Synopsys...
The mPower toolsuite wins Elektronik Product of the Year for Software Tools!!
May 12, 2022
By Shelly Stalnaker Every year, the editors of Elektronik in Germany compile a list of the most interesting and innovative… ...
More from Siemens Digital Industries Software...
Well, That Was Embarrassing!
Apr 29, 2022
What do you do if someone starts waving furiously at you, seemingly delighted to see you, but you fear they are being overenthusiastic?...
More from Max's Cool Beans...

featured video

Synopsys PPA(V) Voltage Optimization

Sponsored by Synopsys

Performance-per-watt has emerged as one of the highest priorities in design quality, leading to a shift in technology focus and design power optimization methodologies. Variable operating voltage possess high potential in optimizing performance-per-watt results but requires a signoff accurate and efficient methodology to explore. Synopsys Fusion Design Platform™, uniquely built on a singular RTL-to-GDSII data model, delivers a full-flow voltage optimization and closure methodology to achieve the best performance-per-watt results for the most demanding semiconductor segments.

Learn More

featured paper

Intel Agilex FPGAs Deliver Game-Changing Flexibility & Agility for the Data-Centric World

Sponsored by Intel

The new Intel® Agilex™ FPGA is more than the latest programmable logic offering—it brings together revolutionary innovation in multiple areas of Intel technology leadership to create new opportunities to derive value and meaning from this transformation from edge to data center. Want to know more? Start with this white paper.

Click to read more

featured chalk talk

10X Faster Analog Simulation with PrimeSim Continuum

Sponsored by Synopsys

IC design has come a very long way in a short amount of time. Today, our SoC designs frequently include integrated analog, 100+ Gigabit data rates and 3D stacked DRAM integrated into our SoCs on interposers. In order to keep our heads above water in all of this IC complexity, we need a unified circuit simulation workflow and a fast signoff SPICE and FastSPICE architecture. In this episode of Chalk Talk, Amelia Dalton chats with Hany Elhak from Synopsys about how the unified workflow of the PrimeSim Continuum from Synopsys can help you address systematic and scale complexity for your next IC design.

Click to read more about PrimeSim Continuum