fish fry
Subscribe Now

Best Little Podcast in Texas

DSP, CES, and The Hapifork

Hello from the Lone Star State! Fish Fry is on the road this week, coming to you from beautiful Austin, Texas, “The Live Music Capital of The World”. Nothing says Texas like a little digital signal processing, so we’re going to chat live with Pierrick Vulliez (CTO and Founder – 4DSP) about FMCs, DSP, FPGAs, and a whole lot more. Wait, what am I doing in Austin while the Consumer Electronics Show is going on in Las Vegas? Never fear, we’ll have a live report from Bryon Moyer, our reporter on the scene at the 2013 Consumer Electronics Show.

Also, I’ve got a surprise for ya’ll, but you’ll need to tune to find out what it is.

Listen to this episode
Download this episode (right click and save)

Fish Fry Links – January 11, 2013

More Information about 4DSP

More Information about 4DSP’s Fiber Optical Sensing Technology

More Information about The Consumer Electronics Show

More Information about The Hapifork

Fish Fry Executive Interviews

Moshe Gavrielov, CEO – Xilinx

Darrin Billerbeck, CEO – Lattice Semiconductor

Lauro Rizzatti, Vice President of Marketing, EVE

Bill Neifert, CTO – Carbon Design Systems

Sean Dart, CEO – Forte Design Systems

Kapil Shankar, CEO – SiliconBlue

Andy Pease, CEO – QuickLogic

Rajeev Madhavan, CEO – Magma 

Paul Kocher, President – Cryptography Research Inc.

Anupam Bakshi, CEO – Agnisys

Dave Kleidermacher, CTO – Green Hills Software

Robert Blake, CEO – Achronix

Jack Harding, CEO – eSilicon

Michiel Ligthart, COO – Verific

Adnan Hamid, CEO – Breker Technologies

Jeff Waters, VP and General Manager – Altera

Luc Burgun, CEO and President, EVE 

Leave a Reply

featured blogs
Aug 16, 2018
Learn about the challenges and solutions for integrating and verification PCIe(r) Gen4 into an Arm-Based Server SoC. Listen to this relatively short webinar by Arm and Cadence, as they describe the collaboration and results, including methodology and technology for speeding i...
Aug 16, 2018
All of the little details were squared up when the check-plots came out for "final" review. Those same preliminary files were shared with the fab and assembly units and, of course, the vendors have c...
Aug 15, 2018
VITA 57.4 FMC+ Standard As an ANSI/VITA member, Samtec supports the release of the new ANSI/VITA 57.4-2018 FPGA Mezzanine Card Plus Standard. VITA 57.4, also referred to as FMC+, expands upon the I/O capabilities defined in ANSI/VITA 57.1 FMC by adding two new connectors that...
Aug 14, 2018
I worked at HP in Ft. Collins, Colorado back in the 1970s. It was a heady experience. We were designing and building early, pre-PC desktop computers and we owned the market back then. The division I worked for eventually migrated to 32-bit workstations, chased from the deskto...
Jul 30, 2018
As discussed in part 1 of this blog post, each instance of an Achronix Speedcore eFPGA in your ASIC or SoC design must be configured after the system powers up because Speedcore eFPGAs employ nonvolatile SRAM technology to store its configuration bits. The time required to pr...