EEJournal

fish fry
Subscribe Now
August 22, 2012

Patently Obvious

Patents, IEEE for EDA, and Sting’s Sister
by Amelia Dalton

Patent litigation – can’t live with it, can’t survive without it. This week we’re checking out some recent rumblings in patent litigation. We’re even bringing in a council person to help mediate the fight. OK, wait – that would be ‘counsel’. My guest is Dontatella Sciuto, the current president of the IEEE Council for EDA. Donatella and I chat about what the IEEE Council for EDA is all about, what project the council plans on attacking next, and why Donatella can call herself Sting’s sister.

Listen to this episode
Download this episode (right click and save)

Fish Fry Links – August 24, 2012

More Infomation about Sidense

More Information about Kilopass

More Information about Kilopass v. Sidense (Fish Fry Episode – September 9, 2011)

More Information about IEEE

Leave a Reply

featured blogs
Training Insights: Cadence Cerebrus Webinar Recording Now Available!
Dec 7, 2023
Semiconductor chips must be designed faster, smaller, and smarter'”with less manual work, more automation, and faster production. The Training Webinar 'Flow Wrapping: The Cadence Cerebrus Intelligent Chip Explorer Must Have' was recently hosted with me, Krishna Atreya, Princ...
More from Cadence...
Q&A With Jyotika Athavale, IEEE Champion, on Advancing Standards Development Worldwide
Dec 6, 2023
Explore standards development and functional safety requirements with Jyotika Athavale, IEEE senior member and Senior Director of Silicon Lifecycle Management.The post Q&A With Jyotika Athavale, IEEE Champion, on Advancing Standards Development Worldwide appeared first ...
More from Synopsys...
A Haunting World Underwater
Nov 6, 2023
Suffice it to say that everyone and everything in these images was shot in-camera underwater, and that the results truly are haunting....
More from Max's Cool Beans...

featured video

Dramatically Improve PPA and Productivity with Generative AI

Sponsored by Cadence Design Systems

Discover how you can quickly optimize flows for many blocks concurrently and use that knowledge for your next design. The Cadence Cerebrus Intelligent Chip Explorer is a revolutionary, AI-driven, automated approach to chip design flow optimization. Block engineers specify the design goals, and generative AI features within Cadence Cerebrus Explorer will intelligently optimize the design to meet the power, performance, and area (PPA) goals in a completely automated way.

Click here for more information

featured paper

Power and Performance Analysis of FIR Filters and FFTs on Intel Agilex® 7 FPGAs

Sponsored by Intel

Learn about the Future of Intel Programmable Solutions Group at intel.com/leap. The power and performance efficiency of digital signal processing (DSP) workloads play a significant role in the evolution of modern-day technology. Compare benchmarks of finite impulse response (FIR) filters and fast Fourier transform (FFT) designs on Intel Agilex® 7 FPGAs to publicly available results from AMD’s Versal* FPGAs and artificial intelligence engines.

Read more

featured chalk talk

Switch to Simple with Klippon Relay
Sponsored by Mouser Electronics and Weidmüller
In this episode of Chalk Talk, Amelia Dalton and Lars Hohmeier from Weidmüller explore the what, where, and how of Weidmüller's extensive portfolio of Klippon relays. They investigate the pros and cons of mechanical relays, the benefits that the Klippon universal range of relays brings to the table, and how Weidmüller's digital selection guide can help you choose the best relay solution for your next design.
Click here for more information about Weidmüller Klippon® Connect SNAP IN Terminal Blocks
Sep 26, 2023
8,396 views