Elk Grove, Calif., March 2, 2026 — Accellera Systems Initiative (Accellera), today announced that its Board of Directors has approved the Standard for IP Abstraction for Clock and Reset Domain Crossing Integration 1.0 for release. The new standard is available for immediate download.
CDC/RDC verification is essential to avoid metastability, glitches, and data reconvergence errors when signals traverse asynchronous clock or reset boundaries. Historically, analysis results and ‘intent’ generated by different tools could not be reused across different EDA tools, forcing re‑runs and manual translation during integration. The new standard defines a vendor‑neutral approach to capture CDC/RDC intent to enable efficient CDC/RDC signoff for IP providers and SoC integrators, across the EDA vendor ecosystem.
“This standard delivers long‑sought interoperability for CDC and RDC verification and will help teams reach SoC signoff faster with greater confidence,” said Lu Dai, Chair of Accellera. “Accellera’s mission is to bring the industry together to solve shared design and verification challenges through open, collaborative standards. This standard for IP abstraction for Clock and Reset Domain Crossing reflects that mission by enabling greater interoperability and reuse across the SoC ecosystem. On behalf of the Board, I want to thank the many volunteers across numerous companies who contributed their expertise, as well as the working group leadership for bringing the industry together to create a practical, market-driven standard.”
The standard addresses a critical industry gap by providing a unified, vendor-neutral approach to handling clock and reset domain crossing across heterogeneous IP and SoC design flows. The lack of a consistent way to exchange CDC/RDC collateral has been a persistent challenge as the industry continues to shift from monolithic design toward IP-based SoC development, often involving IP from multiple internal and external sources verified using different tools and methodologies. The new standard complements existing HDLs and IP-XACT-based methodologies by capturing CDC/RDC information that lies beyond traditional HDL semantics, enabling portable and consistent interpretation across tools. By establishing a common abstraction for CDC/RDC concerns, the standard simplifies IP integration, reduces dependence on shared tools or internal expertise, and helps SoC teams more efficiently integrate and verify complex designs built from diverse IP sources.
“Until now, the industry lacked a common, reliable mechanism to translate CDC/RDC information across different tools,” said Lee Fueng Yap, Chair of Accellera’s Clock Domian Crossing Working Group. “Our goal was to give engineers a practical and repeatable approach to describe and share CDC and RDC intent, regardless of where IP originates or which tools are used. This standard helps teams integrate IP seamlessly, reduces reverification effort, and improves verification confidence as designs scale in complexity. I thank the co-founder of this working group, Dammy Olopade, and all the members of the CDC Working Group for their dedication and close collaboration throughout the development of this standard.”
Accellera will present the standard in an upcoming DVCon U.S. tutorial, “Breakthrough in CDC-RDC Verification Defining a Standard for Interoperable Abstract Model,” that will examine the methodology, scope, and technical foundations of the standard, providing practical context for its application in IP and SoC design flows. The session will take place on Thursday, March 5, from 9:00 a.m. – 12:30 p.m. at DVCon U.S. 2026 (Hyatt Regency Santa Clara, Ballroom D). Attendees can still register to learn directly from working group participants; visit the DVCon U.S. 2026 website for more information.
For more about the Standard for IP Abstraction for Clock and Reset Domain Crossing Integration, visit the Clock Domain Crossing Working Group page.
For a list of supporting quotes from member companies visit the Accellera website.
About Accellera
Accellera Systems Initiative is an independent, not-for profit organization dedicated to create, support, promote and advance system-level design, modeling, and verification standards for use by the worldwide electronics industry. The organization accelerates standards development and, as part of its ongoing partnership with the IEEE, its standards are contributed to the IEEE Standards Association for formal standardization and ongoing change control. For more information, please visit www.accellera.org. Find out more about membership. Follow @accellera on X and LinkedIn or to comment, please use #accellera. Accellera Global Sponsors are: Cadence, ChipAgents, Siemens, and Synopsys.
