The annual DAC CEDA luncheon this year featured Stanford EE Dept. chair Mark Horowitz in a discussion of analog abstraction. Which has always been a tough sell. Which they understand, which is why, at this point, there’s no selling.
Digital productivity has been supported by the existence of standard cells that can be bolted together into a circuit. No more transistor-level design. While that sounds nice for analog, it’s never passed muster because, well, analog is so complex. There are no standard parameters that cross all analog circuits, and nth-order effects matter – heck, they’re sometimes even exploited. To date, no standard-cell methodology has gotten anywhere close to credible with designers.
It’s probably also arguable that there are some job security concerns amongst the analog designer crowd, generally considered an elite and impenetrable bunch. So any practical abstraction approach will realistically have to pass technical muster and then either improve designer productivity without rendering designers redundant or deliver such overwhelming results that management buys in with or without a push from the engineers themselves.
And there are two key roles that such a cell can take on. The first is as a model for validation; the second, more ambitious and elusive, is for synthesis. Yeah, analog synthesis. Be very afraid?
The approach taken in Stanford’s Circuitbook project (at circuitbook.stanford.edu, although, at this point, it’s mostly a skeleton with little actual data), focuses first on validation; once that has been nailed, then they can tackle synthesis (which Prof. Horowitz thinks is probably solvable). They make a distinction between model and implementation, with interfaces forming the heart of the model. The interface itself becomes the published “standard,” with the circuit design for a specific cell implementing that interface.
Of course, many analog functions are highly non-linear, and the approach for the interfaces is to describe things in a linear fashion. But Prof. Horowitz noted that most cells have at least one view or domain in which they are almost linear, even if it’s not voltage over time. For example, a phase-locked loop is non-linear from a voltage standpoint, but if you consider the phase in and phase out, those have a roughly linear relationship.
This alternate view of a linear relationship only applies to the process of validating a model and correlating it with actual silicon. Once you start hooking the models together for simulation, then you operate in the voltage-vs.-time domain so that all of the models can work together.
The other frequent gotcha these days is digitally-controlled analog circuits. This typically means that digital signals change some parameter(s) of the analog circuit. The way they’re approaching this is that a separate analog model is needed for each digital setting. So, for example, a three-bit control interface will result in eight models (assuming no degenerate settings).
You also have to create a port for every physical attribute that matters. If temperature is a consideration, then you need to have a port for it. If the phase of the moon matters, you need a port for it.
This is very much a work in progress, and it’s not clear when it will be available for general use – or even whether it will get traction. But it’s something to keep an eye on…
