feature article
Subscribe Now

Why Universities Want RISC-V

Sometimes It’s Not About The Technology or The Performance

“Learning is not compulsory… neither is survival.” – W. Edwards Deming

New microprocessor designs often emerge from universities. But how often do processors go back into universities? 

It’s a new decade, so a new processor is in fashion. Like hemlines and boy bands, processors rise and fall in popularity. There was the RISC Age. Then the VLIW Era. The Decade of DSPs. Now, it’s all RISC-V. 

There are plenty of reasons for RISC-V’s popularity, but here’s one I hadn’t expected: It’s not ARM. Or x86. Or even MIPS, SPARC, 8051, Clipper, PowerPC, or PDP/11. Among a certain class of customers, RISC-V is the processor of choice almost by default. 

Why? Because nobody owns it. 

This little nugget of wisdom popped up several times over the past year as I’ve interviewed chip makers, software companies, researchers, VCs, startups, and various and sundry members of the tech-curious industry. 

“Why did you choose RISC-V?” 

“Because our research funding required it.” 

“Huh? Your financial backers said you had to use RISC-V? That’s unusual.”

“No, because they said we can’t use a licensed CPU. That left RISC-V, by default.” 

Some version of this conversation happens almost every time a startup is cooperating with a university, especially a European university. The university is happy to collaborate with industry insiders, and they have the grants, the research, and the talent pool to contribute. But there’s a catch. Their participation must be entanglement-free. No proprietary technology and no licensing fees. 

The “proprietary” part leaves out x86 processors, and the “licensing” prohibition eliminates ARM, MIPS, and the other, uh, licensed CPU architectures. That leaves the field pretty much open to RISC-V, today’s predominant open-source processor design. Thus, startups and universities are increasingly basing their work on RISC-V because they have few legal alternatives. 

I’m sure the more ardent RISC-V aficionados will jump in here to say it’s also because RISC-V is so flexible, extensible, powerful, modern, caring, good-looking, etc. But that’s not the case – at least, not with the companies and groups I’ve spoken with. They agree that RISC-V is adequate to their task – they have nothing against it – but that the choice came down to politics and lawyers, not technology, engineering, or performance. They use RISC-V simply because they have to. 

GreenWaves and its GAP8 and GAP9 processors are one example of this. The company collaborates with the University of Bologna in Italy. The chip startup gets significant help from students and faculty at UniBo, but such cooperation requires “non-proprietary architectures,” according to CEO Martin Croome. And that, in turn, helped drive the decision to base GreenWaves’s GAP8 and GAP9 processors on RISC-V. 

Same goes for Tachyum, but in a different way. Its ambitious Prodigy processor can execute several different processors’ instruction sets through emulation, including x86, ARM, and RISC-V. Why RISC-V? Legalities and licensing clearly weren’t deal-breakers, or else x86 and ARM wouldn’t be on the menu. But CEO Rado Danilak says some of his prospective customers are universities, and “academic contracts require RISC-V and prohibit x86. So, we did a RISC-V translator.” 

The underlying rationale for these restrictions lies buried in contracts and funding records, but there are several potential reasons. For one, publicly funded institutions don’t want their research money spent on projects that lock them into a specific product. They may also be hesitant to funnel public money in a way that benefits a commercial for-profit entity. They may fear running afoul of licensing or patent laws, especially since such laws differ from place to place and product to product. Modifying or reverse-engineering a microprocessor is legally tricky, even if it’s just for experimentation purposes. And if you did wind up discovering or developing something from it, what then? You want to make sure your work will be unencumbered before you start, not discover the ugly truth afterwards. 

A processor’s fortune and fame can rise and fall for a lot of random reasons. It’s rarely because it’s the best technical solution for a given task. Sometimes good software support helps sell CPU chips. Sometimes one big customer anoints a winner and others follow suit. Sometimes it’s an unusual business model, or pricing strategy, or just dumb luck. Like any form of evolution, unexpected outside factors can cull the herd and leave the survivors wondering, however appreciatively, what stroke of luck has left them standing. If it comes down to university guidelines or the funding stipulations in some benefactor’s will, so be it. May the hardiest processor win.

2 thoughts on “Why Universities Want RISC-V”

  1. It’s simply not true that there are no legal alternatives to RISC-V if your sponsors require you to use an “entanglement-free” instruction set. There are a number of other choices, including OpenRISC, SPARCv8 (fairly widely used in Europe in the form of the LEON core), SuperH (including SH4 now). Proponents claim that POWER is now “more open than RISC-V” although I was unable to immediately find any implementations on github.

    I’d contend that research projects are actively choosing RISC-V over these alternatives for reasons ranging from technical (various combinations of too complex, too low performance, no room to add new custom instructions, 32 bit-only) to RISC-V’s rapidly growing software ecosystem and pool of people experienced with it.

    1. Of course there are other open-source and/or free choices. Always have been. But today, RISC-V seems to be the default choice among those alternatives, for all the reasons you and I enumerated.

Leave a Reply

featured blogs
Nov 24, 2020
In our last Knowledge Booster Blog , we introduced you to some tips and tricks for the optimal use of the Virtuoso ADE Product Suite . W e are now happy to present you with some further news from our... [[ Click on the title to access the full blog on the Cadence Community s...
Nov 23, 2020
It'€™s been a long time since I performed Karnaugh map minimizations by hand. As a result, on my first pass, I missed a couple of obvious optimizations....
Nov 23, 2020
Readers of the Samtec blog know we are always talking about next-gen speed. Current channels rates are running at 56 Gbps PAM4. However, system designers are starting to look at 112 Gbps PAM4 data rates. Intuition would say that bleeding edge data rates like 112 Gbps PAM4 onl...
Nov 20, 2020
[From the last episode: We looked at neuromorphic machine learning, which is intended to act more like the brain does.] Our last topic to cover on learning (ML) is about training. We talked about supervised learning, which means we'€™re training a model based on a bunch of ...

featured video

Accelerate Automotive Certification with Synopsys Functional Safety Test Solution

Sponsored by Synopsys

With the Synopsys Functional Safety Test Solution architecture, designers of automotive SoCs can integrate an automated, end-to-end BIST solution to accelerate ISO compliance and time-to-market.

Click here for more information about Embedded Test & Repair

featured paper

Top 9 design questions about digital isolators

Sponsored by Texas Instruments

Looking for more information about digital isolators? We’re here to help. Based on TI E2E™ support forum feedback, we compiled a list of the most frequently asked questions about digital isolator design challenges. This article covers questions such as, “What is the logic state of a digital isolator with no input signal?”, and “Can you leave unused channel pins on a digital isolator floating?”

Click here to download the whitepaper

featured chalk talk

The Wireless Member of the DARWIN Family

Sponsored by Mouser Electronics and Maxim Integrated

MCUs continue to evolve based on increasing demands from designers. We expect our microcontrollers to do more than ever - better security, more performance, lower power consumption - and we want it all for less money, of course. In this episode of Chalk Talk, Amelia Dalton chats with Kris Ardis from Maxim Integrated about the new DARWIN line of low-power MCUs.

Click here for more information about Maxim Integrated MAX32665-MAX32668 UB Class Microcontroller