feature article
Subscribe Now

The First Emulators of Spring

New Capabilities Address Verification Challenge

It’s the season of rebirth. The sun is out. Flowers are in bloom. Birds busily build nests while semiconductor verification teams emerge from their long winter hibernation, ready to tool up for the challenges of the next process generation. Billions of unverified gates give shelter to countless bugs awaiting anxious design teams as they prepare for summer’s tape-outs and struggle to bring new software up on wobbly legs.

Yep, the first emulators and prototyping platforms of spring have arrived, and – failing to be greeted with their own shadows – engineers are rejoicing at the prospect of more productive, efficient, and effective verification of their next crop of chip designs.

Cadence and Siemens (formerly Mentor) have both announced substantial upgrades to their emulation and prototyping offerings that promise significant improvements for chip and software design teams. Capacities are up, cycle and iteration times are down, visibility is improved, and cost is… Hah! You didn’t really think we were gonna say the new solutions are cheaper, did you? We are well past the first of April at this point.

First up, Cadence has just introduced their new “Dynamic Duo 2.0” – upgraded versions of their proven Palladium and Protium emulation and prototyping systems. At a high level, the company claims 2x the capacity and 1.5x the performance of previous-generation versions of both. (OK, their press release actually said “1.5x higher performance” but we engineers are picky about math and “1.5x higher” would really mean 2.5x the performance. We think they really meant 1.5x the performance, which would be 50% higher performance.) 

To review the emulator vs prototyping platform scenario quickly, emulators are designed to be used by hardware verification teams trying to squeeze the last bugs out of the RTL in their chip designs. Emulators offer orders of magnitude more throughput than software simulators while still maintaining rapid iteration times for design changes and high levels of visibility for tracing problems into specific signals in the RTL.

Prototyping platforms are similar to emulators, but they are designed primarily for software teams to bring up and test software before the chips are available to run it. These are usually built on FPGAs and offer higher performance, typically very near what the actual final hardware will do. But – when compared with emulators – they bring significant compromise on iteration time (each change iteration to the hardware design using a prototyping platform requires a complete run of synthesis and place-and-route to update the FPGAs) and on visibility into hardware signals (prototyping boards do not have the same capability and simplicity in viewing the internals of the hardware that emulators offer).

For teams designing SoCs along with accompanying software, the progression would typically be from debugging the hardware using emulation, and then, as the hardware design stabilizes, gradually shifting focus to developing and debugging software on FPGA-based prototypes. Cadence has designed their ecosystem to allow a smooth transition from detailed RTL design and debug with software simulation through system-level software simulation, emulation and finally prototyping.

The new Palladium Z2 emulation system is based on a new custom processor designed by Cadence, and the new Protium X2 prototyping platform is based on the massive Xilinx UltraScale+ VU19P FPGAs. These new engines at the heart of the “Dynamic Duo” should deliver big improvements in capacity, throughput, and agility for teams designing multi-billion gate silicon. 

Siemens Digital Industries Software (formerly Mentor Graphics) also made a major verification and emulation announcement, rolling out their next-generation Veloce hardware-assisted verification system. This is Siemens’s first complete, integrated offering combining virtual platform, hardware emulation, and FPGA prototyping technologies into a cohesive verification solution. 

New products announced include Veloce HYCON ( for HYbrid CONfigurable), Veloce Strato+, Veloce Primo, and Veloce proFPGA.  Veloce HYCON is a software virtual platform for verification. Veloce Strato+  is a capacity upgrade to the previous system. Like Cadence, Siemens designed their own custom chip to power the new emulator. In Siemens’s case, the Crystal 3+, a 2.5D chip that Siemens says allows Strato+ to scale to 15 billion gates total capacity, is a 1.5x boost over the existing Veloce Strato system. Siemens claims industry-leading capacity, total throughput, and time-to-visibility with the new emulator.

Moving on to prototyping, the new Veloce Primo is designed for enterprise-level FPGA prototyping. Primo, developed internally by Siemens, also boasts high runtime performance and fast prototype bring-up.  Veloce Primo scales up to 320 FPGAs (the same Virtex UltraScale+ VU19P FPGAs used in Cadence’s new Protium X2 system) and employs a consistent working model with Veloce Strato in terms of software workloads, design models, and front-end compilation technology. This should help teams smoothly transition from emulation to prototyping modes and tasks during their hardware verification and software bring-up cycles. Veloce Primo supports both virtual (emulation offload) and in-circuit-emulation (ICE) use models, allowing flexible tradeoff between accuracy and performance.

If desktop prototyping is a better fit for your needs, Siemens also partners with Pro Design to OEM the Veloce proFPGA system for desktop FPGA prototyping. proFPGA is a modular system that allows you to add capacity as needed, scaling from 40M gates to 800M gates capacity. proFPGA is based on high-end FPGAs including Intel Stratix 10 GX 10M and Virtex UltraScale+ VU19P device.

Veloce Strato+ and Veloce Primo use the same RTL, the virtual verification environment, transactors, and models to maximize the reuse of verification collateral and environment and test content, creating a nicely seamless flow between tools for teams with diverse requirements including hardware, software, and system-level verification across the gamut of verification technologies. 

Which of these offerings would work best for your team probably depends on your existing design and verification environment, as the integration between that and the emulation and prototyping platforms is a key factor in a smooth process. Both of these companies are pursuing similar strategies to address the accelerated verification challenge – emulators based on purpose-built custom processors and prototyping platforms designed around leading high-capacity FPGAs, and verification tool environments aimed at simplifying the transition between phases of the project.

While capacity and throughput are important considerations, the differences a team is likely to realize in small performance differences is far less than what could be consumed with an inconvenient design flow, so choosing an ecosystem that mates well with your design tool flow is key. 

Leave a Reply

featured blogs
May 29, 2022
https://youtu.be/2F6MIuGFcHA Made in my Mini Cooper Convertible Monday: Embedded Vision Summit 2022 Tuesday: May Update: ACM Digital Library, Open RAN Security, Framework Laptop Upgrade, Malcolm... ...
May 26, 2022
Introducing Synopsys Learning Center, an online, on-demand library of self-paced training modules, webinars, and labs designed for both new & experienced users. The post New Synopsys Learning Center Makes Training Easier and More Accessible appeared first on From Silico...
May 25, 2022
There are so many cool STEM (science, technology, engineering, and math) toys available these days, and I want them all!...
May 24, 2022
By Neel Natekar Radio frequency (RF) circuitry is an essential component of many of the critical applications we now rely… ...

featured video

Increasing Semiconductor Predictability in an Unpredictable World

Sponsored by Synopsys

SLM presents significant value-driven opportunities for assessing the reliability and resilience of silicon devices, from data gathered during design, manufacture, test, and in-field. Silicon data driven analytics provide new actionable insights to address the challenges posed to large scale silicon designs.

Learn More

featured paper

Reduce EV cost and improve drive range by integrating powertrain systems

Sponsored by Texas Instruments

When you can create automotive applications that do more with fewer parts, you’ll reduce both weight and cost and improve reliability. That’s the idea behind integrating electric vehicle (EV) and hybrid electric vehicle (HEV) designs.

Click to read more

featured chalk talk

WiFi 6 & 6E: Strengthening Smart Home Enablement

Sponsored by Mouser Electronics and Qorvo

Demands on WiFi are growing exponentially, and our aging standards and technology are struggling to keep up. Luckily, WiFi 6 and 6E represent a leap in WiFi capabilities for our systems. In this episode of Chalk Talk, Amelia Dalton chats with Tony Testa of Qorvo about the ins and outs of WiFi 6 and 6E with their increased speed, capacity, and efficiency.

Click here for more information about Qorvo Wi-Fi® 6 Solution