Long, long ago, at the turn of the millennium, two champions of configurable processor IP – ARC and Tensilica – battled for dominance in that arena with unique processor ISAs and custom tools to aid in creating software-development tool chains for their configurable processors. Synopsys bought ARC in 2011, and Cadence bought Tensilica a couple of years later. Fast forward a decade and suddenly, RISC-V has somehow validated the concept of configurable processors. Consequently, many companies with proprietary processor ISAs have jumped on the RISC-V bandwagon as its ecosystem gathers momentum. For example, Intel announced the development of a third NIOS-V soft processor core for its FPGAs earlier this year (see “Intel Heats Up and Expands its Agilex FPGA family”) and AMD slipstream launched the MicroBlaze V 32-bit modular and configurable RISC-V soft processor core to its early access FPGA developers in November. Now, Synopsys has announced the evolutionary branch of its ARC processor IP into the RISC-V domain with a trio of new ARC-V configurable processor cores.
Synopsys has sectioned its ARC-V core offerings into three segments. The low-end, low-power, 32-bit ARC-V RMX processor IP is scheduled to be available in Q2 of 2024. This segment offers cores with 3- and 5-stage pipelines, and an optional DSP. The 32-bit Synopsys ARC-V RHX processor cores serve real-time applications and feature a dual-issue superscalar pipeline, hardware virtualization, and a functional safety (FUSA) hybrid mode where a pair of ARC-V RHX processors can run in lockstep for ASIL D safety applications or in a dual processor mode for ASIL B safety applications. The 64-bit ARC-V RPX host processor cores are similar to the RHX variants but are 64-bit instead of 32-bit implementations. Additional ARC-V RPX capabilities include a cache-coherent interconnect that permits the design of processor clusters with as many as sixteen processor cores and clusters of processor clusters. The ARC-V RHX and RPX processor cores are scheduled to be available in the second half of 2024.
All of the ARC-V processor cores share the same MetaWare tool chain. ARC acquired MetaWare about 25 years ago and adopted its software development tools for its configurable processor IP. Those same tools, much evolved, still support the existing configurable ARC IP cores and have been extended to support the new ARC-V cores. Because all RISC processor cores share many similarities such as a hardware instruction decoder, pipelined execution, large register files, and a load-store architecture, Synopsys was able to use the existing machinery for the ARC configurable processor cores and developed the ARC-V cores by changing the processor’s instruction decoder, pipeline, and microarchitecture.
Consequently, existing customers for the original ARC processor cores can simply recompile their code for the new ARC-V cores. The MetaWare tool chain is explicitly aware of processor configurability and accepts files from the ARC processor configurator (wittily named ARChitect) to automatically configure the tool chain to generate code for the processor extensions. This same software tool chain also supports the ARC vector DSP and neural processor.
The RISC-V processor core market is fairly crowded these days with players including Andes, Codasip, Imagination, MIPS, Rivos, SiFive, Tenstorrent, Codasip, XMOS, and Ventana. Nevertheless, Synopsys has jumped into this market with both feet by signing up as a Premiere member of RISC-V International, which gives the company a seat on the organization’s Board of Directors, and has joined the RISC-V Technical Steering Committee, which allows Synopsys to participate in the definition of future RISC-V architecture standards.
The crowded RISC-V processor core market prompts two questions about the Synopsys entry. What attracted Synopsys to the RISC-V melee, and how will Synopsys differentiate its processor cores among the many offerings? Matt Gutierrez, Group Director of Marketing for Processor and Safety IP and Tools at Synopsys answers the first question succinctly by saying, “What is attractive about RISC-V is the momentum of the ecosystem.” When asked if Synopsys had joined the RISC-V Software Ecosystem (RISE) Project – a consortium of companies involved with RISC-V ecosystem development, including Andes, Google, Intel, Imagination Technologies, MediaTek, Nvidia, Qualcomm Technologies, Red Hat, Rivos, Samsung, SiFive, T-Head, and Ventana – Gutierrez replied, “No, but we’re certainly aware of it.” I’ll take that to be a solid “Not yet, one thing at a time” sort of answer. There’s the matter of how the Synopsys MetaWare tools fit into the greater RISC-V ecosystem to work out first.
As for the second question regarding the differentiation that Synopsys will be able to offer the RISC-V community, John Koeter, Senior VP of Marketing and Strategy at Synopsys, was not at a loss for words. Since Synopsys jumped into the IP market more than 20 years ago, IP has become “25% of Synopsys,” said Koeter. Unlike most of the competing RISC-V core vendors, Synopsys is a broad-spectrum IP supplier with offerings that include logic libraries, embedded memories, analog IP, wired and wireless interface IP, security IP, embedded processors, and subsystems. Processor cores are only a fraction of the IP blocks in the company’s portfolio. In addition, the company’s IP supports many different process nodes at multiple silicon foundries.
In addition, Synopsys has strong ties to SoC and system design houses through its EDA tool offerings, and IP often comes along for the ride in major corporate-wide EDA and IP purchases. The purchasing decision for a RISC-V core is very different when it’s a part of an overall EDA and IP contract. In addition, Gutierrez points out that, because of the tie-in with its EDA tools, Synopsys can provide a reference design flow for its ARC-V processor cores that’s been validated with Synopsys EDA tools. Put all of these together and it would appear that Synopsys will quickly become a heavyweight supplier in the RISC-V IP market.
The move into the RISC-V arena by Synopsys begs the question about plans by the other major EDA and IP vendor: Cadence. It’s been 10 years since Cadence acquired Tensilica, and a move to bring its Tensilica IP into the RISC-V camp in a way that closely resembles the path that Synopsys is taking with its ARC-V cores seems an obvious response, just as Cadence acquired Tensilica two years after Synopsys acquired ARC. Cadence is certainly aware of RISC-V. The company published a blog about RISC-V processors last year, and its customers are almost certainly running RISC-V processor cores from other vendors through Cadence’s EDA tools already. Very likely, it’s only a matter of time before Cadence jumps on the RISC-V bandwagon as well.