Following my wife, family, and friends (just in case any of them happen to read this by mistake), my first love is digital logic design, and my second is digital logic verification (static analysis, simulation, formal verification… you name it, and I’ll love it).

Unfortunately, our ability to verify our ASIC, ASSP, and SoC designs has fallen behind our ability to… well… design them. As we read in Breaking the Bottleneck: Overcoming the Verification Productivity Gap 2.0 on the Siemens Verification Academy website:

Verification Productivity Gap 1.0 emerged in the 2000s, highlighting the growing disparity between increasing design complexity and verification capabilities. As chip designs advanced, driven by Moore’s Law and the adoption of IP-based methodologies, verification processes struggled to keep pace. This mismatch led to missed bugs, extended time-to-market and significant resource strain, with verification heavily reliant on manual, domain-specific approaches. To address this gap, advancements such as constrained-random coverage-driven verification and formal verification methods were introduced. While these approaches significantly improved verification coverage and efficiency, they did not fully close the gap. Instead, they enabled the industry to maintain equilibrium, preventing the gap from widening further amidst rapidly increasing design complexity.

I must admit that I was quietly confident we had a handle on things, but it now appears we are in the throes of Verification Productivity Gap 2.0, and, wouldn’t you know it, I don’t have anything appropriate to wear! As the folks at Siemens say: “Traditional verification methods, including constrained-random and formal verification, while foundational, can no longer fully address the complexities and challenges of modern semiconductor design.”

Well, bummer!

I was just chatting with a man whose business card is bigger than most (although he doesn’t like to boast). I’m referring to Abhi Kolpekwar, who serves as “Vice President and General Manager of Digital Verification Technologies (DVT) at Siemens EDA, part of Siemens Digital Industries Software” (try saying that ten times quickly).

I’m not saying Abhi is a downer, but he did begin with some bad news, starting with the fact that “first silicon success” is in decline. Things are getting worse, not better, which is the opposite of what we want to see.

First silicon success is declining (Source: Siemens EDA)

In the case of ASICs (which we’ll take to include ASSPs and SoCs), “first silicon success” means receiving the first packaged chips back from the foundry and verifying that they function as intended (I’m still trying to wrap my brain around what “first silicon success” means in the context of FPGAs). If you’d told me that only 32% of ASIC chips worked without requiring a re-spin, I’d have said that was pretty terrible, and it turns out that was the case in 2020. By 2024, this had fallen to only 14%. Eeek! (and I mean that most sincerely). 

The second dimension to this problem is time. By 2024, it seems that 75% of ASIC projects were behind schedule. And the third dimension is people. Abhi tells me that if we examine the level of verification we need to perform today, only 20% of the need is being met with the talent pool currently available in the market. Universities simply aren’t producing enough verification engineers with the requisite skills.

In a crunchy nutshell: complexity is high, time is short, and there aren’t enough skilled people to do the job. So, no problems there, then.

Happily, Abhi also had some good news: the introduction of the Questa One smart verification software portfolio, which can be summarized as “Faster engines, faster engineers, and fewer workloads.”

Questa One: Faster engines, faster engineers, and fewer workloads
(Source: Siemens EDA)

Just to provide an idea of what we’re talking about here, consider Questa One SFV in the lower left-hand quadrant of the image above (where SFV stands for “stimulus-free verification”). This is where we utilize techniques such as static verification and formal verification, which are computationally intensive tasks.

Abhi says that they are combining these tools and techniques, taking all of the static and formal engines “behind the scenes” and then solving the customers’ problems. Take an RTL netlist, for example. Questa One SFV will run the linter, which is a static tool, then run the auto-fixer, which is a formal tool that actually fixes the problems that the linter identified, and then run the equivalency checker to verify that the new, cleaned-up RTL is functionally equivalent to the original RTL (but without any of its potential problems). All of this is covered by a single product license that covers all the tools, and by automatically invoking all the required engines behind the scenes. Pretty tasty, eh?

Or take the Questa One Verification IQ shown in the upper right-hand quadrant of the image above. The initial release of Verification IQ took place in 2023. The new version has advanced in leaps and bounds, boasting all sorts of predictive AI and generative AI capabilities. To provide a simple example, a verification engineer can use natural language to describe a digital condition, and then a generative AI engine can map this into a corresponding system assertion that frontend tools can understand and utilize. Even if the users don’t know how to write and deploy assertions, the system does—just tell it what you want to do and it does it.

Abhi went on to say. “It doesn’t end here. Remember that designers will have captured their design intent in documents such as Microsoft Word and PDFs. We now have the ability to read that design intent directly from those files and convert that into system assertions that our formal engines and simulation engine will honor. This means we are taking your intent, as outlined in your requirement specification, directly into your design through AI and generative AI solutions. This is the sort of advanced capability we are providing with Questa One.”

“Wanger Gadanger!” as my chum Shears used to say (RIP, old friend).

Reading from Questa One’s press release: The Questa One smart verification solution is founded on three core principles:

• Questa One Connected Verification software connects engineers, EDA tools, and verification IP to form a cohesive ecosystem for comprehensive and seamless verification, validation, and test across Siemens’ Questa One, Tessent DFT, and Veloce CS emulation and prototyping systems.
• Questa One Data-Driven Verification software leverages the power of data through AI-powered analytics to bring new insights and to improve verification productivity. Applications of generative, prescriptive, and predictive machine learning technologies enable engineers to achieve the highest levels of verification with the fewest resources.
• Questa One Scalable verification software delivers acceleration and automation second-to-none, with speeds that deliver the fastest verification closure and the highest degree of confidence.

Also in the press release, we read: The Questa One smart verification solution encompasses multiple technical breakthroughs, including the following:

• Questa One Coverage Acceleration software has achieved coverage goals 50x faster than traditional testbench solvers, combining higher/faster coverage results with the benefits of Universal Verification Methodology (UVM) constrained random test generation.
• Questa One DFT Simulation Acceleration software has achieved 8x faster gate-level design for test (DFT) serial pattern simulations, leveraging Questa One Parallel Simulation software, and is tightly integrated with the industry-leading Tessent Streaming Scan Network (SSN) architecture.
• Questa One Fault Simulation Acceleration software has delivered 48x faster performance and supports both functional safety and DFT fault simulation applications. It uniquely supports the User Defined Fault Modeling (UDFM) capability in Tessent.
• Questa One Stimulus Free Verification software empowers engineers to achieve new levels of productivity. Its unique approach of combining engines and unifying applications has been shown to reduce overall processing times from over 24 hours to under 1 minute on complex open-source SoC-level reference designs. The integration of 20 different stimulus-free analyses, AI, and automation delivers new solutions such as linting with auto-correction and generative AI SVA property creation and verification. 
• Questa One Avery Verification IP software is based on Avery’s high-quality VIP and high-coverage Compliance Test Suites (CTS). Protocol-aware debug and protocol-aware coverage analytics help increase productivity, and accelerated VIP enables the same CTS, testbench, and stimulus on Questa One Sim to be reused on Veloce CS emulation and prototyping systems.

When I think of how proud we all were of our verification technologies just five or ten years ago, and how dull they seem in comparison to today’s Questa One, it makes me wonder what we can look forward to in five or ten years’ time. What say you? Do you have any verification-related thoughts you’d care to share with the rest of us?