feature article
Subscribe Now

RISC-V Fast Tracks Simpler Extensions

More Hope for Erstwhile CPU Designers

One of the charming aspects of RISC-V is that it’s so… flexible. As an open-source processor specification, absolutely anyone can use it, modify it, and commercialize it. There are no licensing fees, no rules, and no compatibility test. It’s the Wild West of processors. Up to a point. 

If you want to call your processor RISC-V, however, you have to follow the rules. The name “RISC-V” is trademarked, and there are also trademarked variations, subsets, profiles, and extensions that are all managed by the Switzerland-based RISC-V International organization. So, you’re welcome to ride off roughshod and blaze your own trail, pardner, but if you want to mingle with civilized company, you’ll have to tidy up and follow the rules. 

One of those rules governs how you propose new additions to the baseline CPU architecture. Again, you’re free to create your own add-ons any dadgum way you like, but if you want them to become part of the official RISC-V canon, there are procedures to follow and papers to fill out. It’s a lengthy process, but one that ensures that all officially approved extensions meet certain criteria and play nice with all the other extensions. 

That too onerous for you? Well, maybe there’s a middle ground. Starting today, if your proposed extension is simple enough, minor enough, and well-behaved enough, you might get special dispensation to “fast track” its approval. You’ll still have to dot some i’s and cross some t’s, but it’ll all be over much sooner and you can be on your way. 

According to Mark Himelstein, CTO at RISC-V International, the new fast track program includes all the same steps as the usual path – he hesitates to call it the slow track – but they just go faster. The idea is to allow relatively simple and uncontroversial extensions to get checked out and checked off without taking up so much time. 

As an example, the proposed new ZiHintPause instruction isn’t nearly as complicated as a complete suite of floating-point operations or a package of AI-acceleration extensions. The latter two are currently plodding their way through the review and verification process. But ZiHintPause is just a single instruction with a comparatively trivial function. It tells the CPU that this might be a good time to enter low-power sleep mode. Whether the hardware actually does anything at all is left up to the chip implementer. It’s just a hint, not a command. Apart from assigning it an opcode and documenting its intended purpose, there wasn’t a lot to do. Hence, its quick approval.

Himelstein says a fast-tracked proposal should take somewhere around two months or so to get approved, give or take a few weeks. There’s still the 45-day public review process, where interested parties can provide feedback (or not) if they foresee a problem. “That doesn’t scrunch down,” he says. But there’s less documentation required and lower hurdles for proof of concept. 

The overall procedure doesn’t change, either. All RISC-V extensions must be proposed by two or more dues-paying RISC-V members, who then form a committee to “own” that extension and shepherd it through the approval process. This minor hurdle prevents random citizens from spamming headquarters with every new idea. (They’re still free to implement extensions on their own, without any form of approval.) The relevant RISC-V committees then meet, discuss, revise, and approve the proposal, often without ever disturbing upper management. “We trust our committees,” says Himelstein. “We try to push power down. If we centralize everything, it slows down.” 

The ZiHintPause instruction was approved, by the way, making it the first official RISC-V extension to make it through the fast track process. Himelstein says there are at least a dozen more in the pipeline. So, look for RISC-V to keep changing. Just faster.

Leave a Reply

featured blogs
Sep 28, 2022
Learn how our acquisition of FishTail Design Automation unifies end-to-end timing constraints generation and verification during the chip design process. The post Synopsys Acquires FishTail Design Automation, Unifying Constraints Handling for Enhanced Chip Design Process app...
Sep 28, 2022
You might think that hearing aids are a bit of a sleepy backwater. Indeed, the only time I can remember coming across them in my job at Cadence was at a CadenceLIVE Europe presentation that I never blogged about, or if I did, it was such a passing reference that Google cannot...
Sep 22, 2022
On Monday 26 September 2022, Earth and Jupiter will be only 365 million miles apart, which is around half of their worst-case separation....

featured video

PCIe Gen5 x16 Running on the Achronix VectorPath Accelerator Card

Sponsored by Achronix

In this demo, Achronix engineers show the VectorPath Accelerator Card successfully linking up to a PCIe Gen5 x16 host and write data to and read data from GDDR6 memory. The VectorPath accelerator card featuring the Speedster7t FPGA is one of the first FPGAs that can natively support this interface within its PCIe subsystem. Speedster7t FPGAs offer a revolutionary new architecture that Achronix developed to address the highest performance data acceleration challenges.

Click here for more information about the VectorPath Accelerator Card

featured paper

Algorithm Verification with FPGAs and ASICs

Sponsored by MathWorks

Developing new FPGA and ASIC designs involves implementing new algorithms, which presents challenges for verification for algorithm developers, hardware designers, and verification engineers. This eBook explores different aspects of hardware design verification and how you can use MATLAB and Simulink to reduce development effort and improve the quality of end products.

Click here to read more

featured chalk talk

ROHM Automotive LED Driver IC

Sponsored by Mouser Electronics and ROHM Semiconductor

There has been a lot of innovation in the world of automotive designs over the last several years and this innovation also includes the LED lights at the rear of our vehicles. In this episode of Chalk Talk, Amelia Dalton chats with Nick Ikuta from ROHM Semiconductor about ROHM’s automotive LED driver ICs. They take a closer look at why their four channel outputs, energy sharing function, and integrated protection functions make these new driver ICs a great solution for rear lamp design.

Click here for more information about ROHM Semiconductor Automotive Lighting Solutions