The recent downturn in the semiconductor industry, unprecedented in its magnitude and duration, has forced application specific standard product (ASSP) vendors to improve the fiscal efficiency of their product development processes and capabilities, with the intent of maximizing return-on-investment (ROI). Improving development capability and efficiency will lower non-recurring costs, and will also lower the cost of goods sold (COGS), resulting in improved profitability. Successful ASSP companies understand the fiscal benefit of strong design capability and actively seek opportunities for improvement.
Unfortunately, Moore’s Law works against development efficiency. Increasing device complexity enabled by increasing transistor density is driving development costs up faster than efficiency tools such as EDA software can bring them down. As a result, fewer ASSP product proposals can successfully demonstrate a reasonable ROI and therefore are not funded.
The Valley of Death: Defined by Profitability
High-level product positioning for ASSPs is relatively straight forward. Successful products generally strive to take one of two positions: operational excellence (the lowest cost-per-function), or product leadership (the highest features and/or capabilities). Dynamic random access memory (DRAM) is a good example of a cost-positioned product. Profit margins are low, but profitability is high due to large volumes. For this type of product, vendors continually focus on reducing COGS. On the other hand, microprocessors are a good example of a feature-positioned product. Prices are reflective of capabilities, with a premium going to those products that are first to market. Volumes are lower than DRAMs, but profit margins are higher, again resulting in higher profitability. It is this profitability curve that defines the product development “Valley of Death.”
This Valley of Death has been widening as the cost pressures of non-recurring development costs increase dramatically. According to the Fabless Semiconductor Association (FSA), a 90-nm ASIC can cost $30 million to develop. Add to this the expenses associated with intellectual property (IP) development, and a company practically needs a $1 billion target market to justify a product. These increasing costs conspire to throttle the development of new products, especially those that are speculative and cannot demonstrate the volume required for adequate profitability. For semiconductor vendors, this is a worst-case scenario, compromising revenue diversity, and working directly against the desire to be first to market.
Breaking out of the valley of death is possible. Clearly, there are semiconductor vendors who are successful, even in today’s semiconductor market. Their strategy for success focuses on ROI risk management by identifying, understanding, and managing underlying expense drivers. Vendors can implement integrated circuit (IC) development strategies that match the volume risk. By doing this, a company can position itself to reap the rewards of investing in applications that may appear to be in the Valley of Death, but can actually emerge as profitable.
Expenses Driven by Development
According to a study done for the EDA industry, more than 50 percent of development engineering labor expense is spent on functional verification, and therefore extracting efficiency in this area can have a tremendous impact. Using additional data from the EDA industry, validating in hardware has shown to be two orders of magnitude more efficient than validating in software, which is the typical method for ASIC development. Therefore, validating in hardware offers much better cost efficiency, and is a benefit that FPGA users are realizing today.
Anecdotally, overall FPGA-based development can be 35 to 50 percent more efficient than ASIC-based development. This metric is based upon empirical data from the EDA industry, as well as Altera’s own experience. At 35 percent, one dollar of ASIC development translates to sixty-five cents of FPGA-based development. Using this ratio, the development-cost benefit using programmable logic devices can be quantified.
What Is Too Expensive?
The development cost benefit of using programmable logic materially impacts time-to-profit and time-to-market. A simple analysis of an ASIC project that has $5 million of development costs (typical of costs encountered using a mature 0.18 micron process) shows that an alternative device costing twice as much per unit as the ASIC can be more profitable in quantities up to 57,000 units (assuming a 35 percent gain in development cost efficiency). A device that costs three times as much per unit as the ASIC can be more profitable in quantities up to 30,000 units. In summary, an alternative technology that saves 35 percent in non-recurring development costs will be more profitable than an ASIC in volumes up to20,000 units per year over a three-year life span, even if its variable cost per unit is two to three times more expensive than the ASIC.
Ideally, programmable logic would be that alternative technology, making the decision very straightforward. Unfortunately, programmable logic that is not pad limited can be ten times or more expensive than a comparable ASIC, but there is a viable solution. That solution utilizes structured ASICs, often within 50 percent of the cost of a comparable standard-cell ASIC. Using an FPGA during hardware development and a structured ASIC during production can easily achieve the cost target required to drive profits in low- to mid-volumes.
Semiconductor vendors must evaluate their projects in terms of volume. Economy of scale requires volume to be the basis for all other fiscal calculations. Too often, especially in a hyper-growth environment, vendors are fixated on time-to-market rather than overall profits. This causes decisions to be made on speculation rather than on fiscal fundamentals. Unfortunately (or fortunately, depending on your perspective), the current economic environment dictates that vendors focus on fiscal fundamentals first.
The most successful semiconductor vendors today demonstrate best-in-class design capabilities. This in turn creates efficiency in their development processes, demonstrated by shortened development cycles, spin-less ASICs, and minimized-die area. Successful vendors know that their profitability depends upon superior execution as measured by time and expense.
The combination of FPGAs and structured ASICs serve to minimize development time and expense. This benefit comes with a tradeoff: higher cost of goods sold. However, as we have shown, even with COGS two times that of the equivalent standard-cell ASIC, applications that run in the 100,000 unit range will be more profitable using an FPGA and structured ASIC. With this as the basic underpinning of a project, qualitative factors such as ease of use and minimal conversion risks allow vendors to make trade-offs among structured ASIC vendors.
Altera has developed HardCopy® structured ASICs to be netlist and timing compatible with Altera® FPGAs. This means that the same development tools used for the FPGA are used for HardCopy, and Altera ensures pin and timing compatibility. Therefore, users are isolated from the risks associated with converting an FPGA design to another technology. With these benefits, Altera’s HardCopy enables semiconductor vendors to tap into new or emerging markets without the fiscal risk associated with traditional standard-cell ASIC development. In this way, vendors can broaden their product portfolio, alleviating the higher-level corporate risk associated with being tied to a single market or application while returning profits to shareholders.