Interest in FPGA reliability is not restricted to SEU environments. The US critical infrastructure, for example, often demands 24/7 operations and thus hi-reliability is frequently sought and very few, if any, of the infrastructure components are in SEU environments.

System failures are largely attributed to software-level errors such as unexpected input values, timing violations, and I/O shortfalls. To decrease the probability of system failure, many specialized, checking functions can be performed during runtime to make the software error-resilient. However, system performance suffers because the checking functions consume processor cycles that would otherwise be used for the mission … Read More → "Migrating FPGA Virtual Gates to MROM Reduces Reliability Risk"

High-reliability design considerations are fast becoming an art that system engineers have to undertake very early on in the design process, often beginning with a designer’s choice of system silicon. For designers seeking flexibility and time-to-market advantages, high-reliability FPGAs are a good choice. However, not all high-reliability designs are created equal. There is a broad spectrum of high-reliability designs out there today, from space-bound satellites to anti-lock braking systems in our ground-based vehicles. While there are obvious similarities between these two types of systems, there are also some key differences, all of which become important … Read More → "FPGA Reliability in Space-Flight and Automotive Applications"

Most of us know Moore’s law to have only one independent variable – time. Mr. Moore predicts that, as time goes by, the complexity of our electronic designs increases exponentially. One thing Mr. Moore never mentioned in public, however, is the secret second factor. Aerospace engineers have long been aware that Moore’s law has a little- known term in the denominator. This factor is something like “one plus altitude squared.” As your design gets farther from the ground, the fabrication technology goes back in time along the line of progress. Until recently, by … Read More → "Space Silicon"

The TCP/IP protocol suite is the de facto worldwide standard for communications over the Internet and almost all intranets. Interconnecting embedded devices is becoming standard practice even in device classes that were previously stand-alone entities. By its very definition, an embedded architecture has constrained resources, which is often at odds with rising application requirements.

Achieving wire-speed TCP/IP performance continues to be a significant engineering challenge, even for high-powered Intel™ Pentium™-class PCs. In this article, we’ll discuss the per-byte and per-packet overheads limiting TCP/IP performance and present the … Read More → "Considerations for High-Bandwidth TCP/IP PowerPC Applications"

When I was a kid, my Dad had a big’ol vacuum-tube audio amplifier. It was massive, heated the room, and took several minutes to “warm up” before it was ready for duty. Sometimes the transformers would hum along with the music, which was OK if the tune was in a key that was a multiple of 60Hz. To me, the thing seemed a bit clunky compared with the transistor-based mainstays of the day. When I asked Dad about the amp, he’d always reply “Well, son, they used to make them all that … Read More → "Crossing Over"

Myopia is one of the few unfortunate consequences of specialization. While focus, refinement, and evolution deliver us some of our most impressive efficiencies, indiscriminate rule breaking is more often the root of spectacular progress. We walk along in our well-walled worlds day-to-day, carefully categorizing concepts like “Field Programmable Gate Array,” “Structured and Platform ASIC,” and “Programmable System on Chip,” and we forget to color outside the lines occasionally, just to see what happens.

Actel announced its new Fusion architecture this week, and somebody clearly went a little crazy with the coloring … Read More → "Actel Adds Analog"

Back when FPGAs were simpler devices, in-system debug was sufficient. Turning a re-spin in response to a specification violation found on the bench was a quick and easy process. Life was great, since re-spins were essentially “free”. This is no longer the case today. One company recently spent three entire months trying to incorporate just one late-coming specification change, because the design team encountered difficulties meeting requirements after making that single change. This is not an isolated case; increasingly painful re-spins are no longer a rare occurrence. Clearly, this particular re-spin cost the customer dearly. … Read More → "A New Spin on FPGA Re-spins"

“It was the best of times, it was the worst of times,
it was the age of hardware design, it was the age of programming,
it was the epoch of synthesis, it was the epoch of compilation,
it was the season of optimization, it was the season of acceleration,
it was the spring of flexibility, it was the winter of automation,
we had everything before us, we had nothing before us,
we were all going direct to Hardware, we were all going direct
the other way–in short, the period … Read More → "SRC Code"

What has over two million real ASIC gates, runs at over 200MHz with twenty levels of logic, burns about the power of a cell-based ASIC, and is economically feasible to deploy even in mid-to-small volume production? The answer is “Not an FPGA”. While these specs may sound close to the marketing picture painted by programmable logic vendors, there is a vast gulf between the brochure and real-world performance in an average application. Structured and platform ASICs, however, can realistically reach these goals in your average application, and getting design teams to understand that fact is one of … Read More → "LSI Logic’s Leverage"

From before my kids were born until after they were grown and graduated, it was a June ritual. Twenty-one times in all, I made my annual pilgrimage to the Design Automation Conference (DAC), perhaps the most misunderstood massing of technology professionals our industry has to offer. DAC is “Burning Man” for the left brain – a mysteriously gravitational gathering that inexplicably pulls people from around the globe to one central location in non-consensual celebration of the unclear.

This year, the 42nd annual DAC was held in Anaheim California. It featured 240 exhibitors, 60 of whom were showing … Read More → "Ditchin’ DAC"