Myopia is one of the few unfortunate consequences of specialization. While focus, refinement, and evolution deliver us some of our most impressive efficiencies, indiscriminate rule breaking is more often the root of spectacular progress. We walk along in our well-walled worlds day-to-day, carefully categorizing concepts like “Field Programmable Gate Array,” “Structured and Platform ASIC,” and “Programmable System on Chip,” and we forget to color outside the lines occasionally, just to see what happens.
Actel announced its new Fusion architecture this week, and somebody clearly went a little crazy with the coloring book. When we digitally-blinded folks consider the construction of future “Systems on Chip” we are all too happy to overlook the analog part of our system. Somewhere in the back of our minds, we know that the real “System” includes lots of things we typically don’t discuss, like power supplies, mechanical parts, antennae, and other components designed by people who probably flunked out on Karnaugh maps and had to settle for one of the less prestigious branches of engineering. Disregard the fact that we never quite completely understood Laplace transforms or that we still shiver at the idea of a transistor that’s lost its way somewhere between saturation and depletion. Deep down, we probably feel safer pretending that analog really isn’t involved.
Now that Actel has announced its upcoming Fusion family of FPGAs with interesting amounts of built-in analog, we must all reconsider our definitions and re-establish our comfort zone. Fortunately for us, Fusion also carries with it a well-conceived design environment and methodology that will simplify the task of assembling a single-chip, mixed-signal FPGA system with built-in volatile and non-volatile memory. Unfortunately for us, we’ve got “6 to 9 months” to get used to the idea.
Actel is taking advantage of the higher voltages and other characteristics of its flash-based ProASIC FPGA technology to gain serendipitous benefits in going mixed-signal. The wider voltage rails obviously allow greater swing and accuracy in analog components of the device, and simplify analog connectivity to the outside world by often eliminating the need for voltage scaling. (I know, digital guys, we’re talking about analog and it’s scary, but we’ll be safely back to bits in a paragraph or so.) Actel claims that their triple-well process also reduces noise in analog portions of the circuit, creating isolation from the switching noise of the digital domain.
Furthermore, Actel’s Fusion concept goes a great distance beyond a new FPGA family with analog added in. True, the new family boasts a unique combination of programmable FPGA fabric, volatile and non-volatile memory, soft and external processor integration and programmable analog, but it also comes bundled with a multi-tiered design philosophy that will offer design teams a simple, mix-and-match, IP-based design flow. Actel’s Fusion design philosophy is based on a layered scheme of plug-and-play IP, which Actel calls a “Fusion Technology Stack”.
At the lowest level of the architecture, which Actel calls “Level 0”, are “Fusion peripherals” which are IP blocks ranging from hard-wired IP to programmable analog blocks to soft-programmed FPGA blocks. These peripherals can be selected from a library of Actel and third-party provided IP, or created by the user. Connecting these components together is the “Fusion Backbone” (“Level 1” for those following along in our diagram) which is an intelligent bus structure capable of managing peripheral configuration and controlling peripheral behavior via a low-level state machine integrated into the backbone.
One level up from the Fusion Backbone, is Level 2, the “Fusion Applet”. An applet is a higher-level building block implementing a function based on FPGA gates, and communicating with peripherals through the backbone. Actel has designed the applet structure as the primary IP integration level, with a well-defined interface for plug-and-play use of IP from a variety of sources. The robustness of this level of Actel’s environment, the degree of complexity involved with integrating new IP applets into the Fusion framework, and ultimately Actel’s success in providing a rich library of applets through original development and third-party partnerships is likely to be a key deciding factor in Fusion’s success in the market.
Sitting atop the Applet layer, at Level 3 are what Actel refers to as “System Applications”. These applications are generally user-supplied and are built in FPGA gates from groups of applets working together. Actel claims that System Applications will allow complete FPGA-based systems to be created without any HDL coding. Dispensing with the HDL requirement opens up the new Fusion platform to a much wider audience, and brings single-chip system design within reach of the masses of embedded system design teams, who might have previous experience only with board-based systems.
Leveraging their recently announced partnership with ARM, Actel will be offering an ARM7 soft-core processor in Fusion along with its existing 8051 microcontroller. The Fusion architecture is designed to be compatible with external processors/MCUs as well, giving design teams the flexibility to choose a processing environment that best suits the needs of their design. The combination of the IP-based hardware configuration environment and industry-standard processors and programming environments opens up Fusion to a broader and more diverse audience than the typical platform FPGA.
What does this announcement mean for Actel and the industry? There are still a few too many variables to tell for certain. We don’t yet know density ranges or pricing for these devices, and those factors will be huge determiners of the types of applications that can take advantage of Fusion. As mentioned earlier, we also don’t yet have a clear picture of the diversity and completeness of IP support for the Fusion ecosystem. The robustness, completeness, and availability of IP a will drive what industries and applications can capitalize on the plug-and-play simplicity promised by Fusion’s design approach. The density range will determine the complexity of applications that can consider Fusion, and Actel’s pricing will determine the volume ranges in which Fusion is a viable solution.
Actel, however, is clearly continuing on a well-conceived strategy to flank the FPGA competition with innovative alternative approaches rather than following blindly in the footsteps of larger FPGA companies. Actel is driving competition to innovate by providing features not available with traditional SRAM FPGA technology. These features, including non-volatility, embedded flash, and now mixed-signal enrich the market with fresh options, and tack away from competitors. This forces the competition to either cover by trying to follow suit, or risk missing out on major market opportunities if Actel’s bets prove accurate.
As the electronics industry braces itself for the self-created shock of the coming decade, a new and interesting texture is emerging in the market. FPGA companies blazed a single-track trail in bringing programmable hardware to the mainstream. Now that a beachhead is established, that single track is turning into a major freeway with a variety of diverse destinations and options. As in many industries, bold innovation in FPGA often comes from the smaller, more nimble companies with less market share to risk and more to gain. Actel seems all too happy to play that role in programmable logic, which serves both them and the market well. Now that Fusion is out of the bag, it will be fun to watch the world respond.