High-speed system interconnects have a large impact on integrated circuit (IC) package design. High-speed connectivity requires fabrication of packages that are able to support very fast varying, broadband signals with good signal integrity (SI).  Based on Moore’s law, on-chip clock frequency doubles every 18 months and the intrinsic delay of the gate decreases exponentially to a few picoseconds (ps). Increasing I/O counts add another element to this equation. Rent’s rule states that the number of I/O will double in the next ten years, which means that there will be a lot … Read More → "FPGA Packaging and Signal Integrity"

Don’t be fooled by quarterly results.

Lattice Semiconductor has been on a new-product rampage for the past two years.  Beginning with their alliance with foundry partner Fujitsu, the company has put up an impressive streak of successful new product introductions.  From the company’s first low-cost FPGA, the “El Cheapo” Lattice EC, to the just-introduced XP2 90nm non-volatile family, Lattice seems to have gotten its engineering act together in a big way.

Why haven’t their financial results shown it yet?  In the FPGA business, the … Read More → "Lattice Leaps Forward"

For years, we had just “FPGAs.”  We didn’t have today’s high-end, low-cost, value-based, platform-enabled, I/O optimized, low-power, DSP-enhanced, SerDes-enriched flavors.  The very nature of FPGAs was to be generic.  They were, after all, reprogrammable devices that could tackle any task assigned to them (provided, at the time, that task didn’t require more than about 30MHz performance or more than a few thousand look-up-tables or any memory or even the merest modicum of power efficiency.)  In other words – glue logic.

From those humble beginnings, … Read More → "Merging Lanes"

Most of us just press the button.

It’s easy to just push the button for synthesis and place-and-route and forget that there is an awful lot of complicated stuff going on behind the scenes from the time we hand our new, shiny HDL over to our FPGA design software, head out for a coffee break, and return to our desk to get the happy message back that our run is all finished and our design fit and routed and met… oh, wait – 576 timing violations.  Suddenly, things are not so happy anymore. </ … Read More → "Beyond the Go Button"

Anybody familiar with Altera FPGAs knows the GX designation.  It’s the suffix that goes on when the family gets upgraded with high-speed serial transceivers.  First we had Stratix, then Stratix GX.  Next, at 90nm we got Stratix II and then Stratix II GX.  Now the company has announced their 65nm lines.  There’s Stratix III, now Cyclone III, and we’re waiting for the GX and… What’s this?  Arria?  90nm again? Confused?  We’ll sort it out for you.

Altera and … Read More → "Serial Commodotization"

If the chain of tools comprising your design flow works flawlessly in getting your hardware ideas to silicon quickly, then the value of that flow is priceless. However, if one or more of the links in that chain is broken or corrupted, then the value of that flow plummets.. Whether you are thinking about assembling a new design flow or auditing your existing flow, this paper covers methods for improving the effectiveness of that chain of tools.

Introduction

Design flows tend to grow in complexity over time. These flows consist of commercial tools … Read More → "The Value of a Complete FPGA Design Flow"

We all know the basics of Moore’s law, right?  Every new process node brings a bounty of the three “Ps” – Price, Performance and Power.  Most of us can recite them like the alphabet.  Missing from our recitation, however, might be some other things that come with a new process node – Lead, Mercury, Cadmium, Chromium, PBBs and PBDE – now THOSE will taste nice on your breakfast cereal.  Electronic waste is a major polluter, and, thanks to Moore’s Law, we always have better, faster, cooler products to offer the … Read More → "It Isn’t Easy Being Green"