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Beyond the Go Button

Taking More Control of FPGA Design

Most of us just press the button.

It’s easy to just push the button for synthesis and place-and-route and forget that there is an awful lot of complicated stuff going on behind the scenes from the time we hand our new, shiny HDL over to our FPGA design software, head out for a coffee break, and return to our desk to get the happy message back that our run is all finished and our design fit and routed and met… oh, wait – 576 timing violations.  Suddenly, things are not so happy anymore. 

For many – who don’t venture too near the edge of the rather large envelope of FPGA capability — this situation seldom arises.  Those engineers can go about their daily business, treating FPGA design as a mostly black-box process.  Start pushing the parts to their limits, however, of utilization, performance, or power consumption, and you’ll find yourself faced with the need to become better acquainted with your design than the web-downloaded, automated, you-don’t-need-to-understand-it-all, approach will permit. 

65nm FPGAs are now a reality.  This week, Xilinx announced that they have been shipping 65nm FPGAs for one year. (Can it possibly be a year already?)  In fact, both Xilinx and Altera have long since announced 65nm lines (including Altera’s recent announcement of the first low-cost 65nm family – Cyclone III) – and more are sure to follow.  With 65nm technology, the potential complexity and speed of a design loaded into a high-end FPGA reach staggering proportions.  If you try to take much of that capability out for a test drive, you’ll find yourself needing to abandon the blissful ignorance afforded by automation and get acquainted with your design in new and interesting ways. 

For that, you’ll probably want something like Xilinx’s PlanAhead tool.  Xilinx acquired the PlanAhead product a few years ago from a startup called Hier Design.  Originally, PlanAhead brought ASIC-class floorplanning to the world of FPGA design.  Why would FPGA designers want an ASIC-class floorplanning tool?  Good question – we were wondering that ourselves.  For a long time, it seems, most didn’t.  In fact, even in the ASIC design world, designers didn’t flock to floorplanning because they thought it was fun or particularly interesting.  They usually floorplanned as a measure of last resort.  When all the synthesis directives and scripts and constraints had been squeezed to their limits, and the design still wasn’t meeting spec, it was time to bring in the floorplanner.  The team would reluctantly fire up the floorplanning tool, move the part of the PCI block that was waaay over there on the left by the I/Os back toward the middle where the rest of the macro was located, slide that one multiplier over closer to the RAM, regroup a few straggler instances with the rest of their flocks and voila! – timing woes disappeared like magic.

When Xilinx acquired Hier Design, they probably had a pretty good idea that FPGA design would eventually reach a point where that same scenario would frequently play out.  Over the years since that acquisition, they’ve worked to make the tool more useful for a variety of related tasks, and it has now become a cockpit of sorts for all kinds of useful “under the hood” operations like running the design multiple times through PAR (place and route) and synthesis with different options and comparing results, managing pin assignments, and applying placement groupings and constraints for timing purposes, to facilitate team design, or to take your crack at partial reconfiguration – still the extreme sport of FPGA design. 

Announced about a month ago, the latest release of PlanAhead – 9.1i, is more robust than its predecessors, adding new capability for pin assignment and improved placement constraint management.  When you consider that the new 65nm families are available with user I/O counts poking up into the 1200-pin range, plain-old Excel-based pin assignment strategies may no longer cut it.  When you also consider the intimate relationship between pinout and placement for maximum performance, it makes sense to co-locate the pin assignment and floorplanning capabilities in a single tool.

Xilinx points out that PlanAhead makes their suite of test designs speed up by an average of 10-15%.  That’s about a speed grade to you and me.  They also claim that real designers with larger, real-world designs often do significantly better.  While it is true that the capabilities of automated place-and-route are improving with every release, the challenges posed by the higher complexities of designs with new process generations largely balance out that progress.  With greater complexity, however, the potential for improvement with a little common design sense applied by a human with a tool like PlanAhead becomes much greater.  Our ability to perceive design problems and intuit solutions at a high level is still quite a bit better than the best automated placement and routing algorithms.

PlanAhead’s new pin assignment capabilities are also none too soon, given the already daunting task of creating reasonable I/O assignment and dancing on the balancing wire between on-chip timing constraints and board-level timing and signal integrity issues.  The new capability, dubbed “PinAhead”, provides both semi-automatic and fully-automatic I/O pin placement in a graphical, gui-based, drag-and-drop environment.  Combined with the floorplanning capabilities already present in PlanAhead, you can sensibly co-locate groups of related ports with the on-chip design blocks with which they communicate.  You can also export the pinout in a variety of formats compatible with major board design tools.  This facilitates accurate communication of the huge load of data that has to move between the FPGA and PCB design environments. 

PinAhead gives a graphical view of both the package and die views of the design, as well as a spreadsheet-style pin map.  It also provides hierarchical browsers for both the I/O ports in your design and the package pins available.   The interface is intuitive and easy to navigate, and, as a bonus, the package view looks kinda like a giant “Bejeweled” game.  In this game, however, the matching halves of differential pairs don’t disappear if you line them up – they just work better. 

PlanAhead also still gives you a nice set of capabilities in iterating your design and managing team design by allowing you to constrain and lock down important chunks of logic while you continue working on others.  By using the available constraints to fix and group logic, you can avoid having to re-optimize parts of your design that were already stable during subsequent iterations.  This is also where you manage the task of allocating special areas for partial reconfiguration – if you just have to prove that you’re the hippest FPGA designer in the house.

While 65nm FPGAs may not have found their way onto your latest board just yet (they’ve only been around for a year, you know), they are definitely coming your way soon.  When they do – a tool like PlanAhead may be just what you need to put a leash on some of that newfound functionality and make it do your bidding.

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