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Lattice Leaps Forward

90nm XP2 a Fit Sequel

Don’t be fooled by quarterly results.

Lattice Semiconductor has been on a new-product rampage for the past two years.  Beginning with their alliance with foundry partner Fujitsu, the company has put up an impressive streak of successful new product introductions.  From the company’s first low-cost FPGA, the “El Cheapo” Lattice EC, to the just-introduced XP2 90nm non-volatile family, Lattice seems to have gotten its engineering act together in a big way.

Why haven’t their financial results shown it yet?  In the FPGA business, the time from winning a socket on a customer’s board to realizing revenue from volume shipments can be 18 months or more.  Selling lots of development kits and samples doesn’t do much for the bottom line initially.  What it does translate into, however, is good potential for the future.

The newest entry in their programmable logic portfolio, Lattice XP2, is a sequel to their highly successful non-volatile Lattice XP line.  In addition to rolling the product up to the latest 90nm technology (and blazing some new trails implementing flash in 90nm), the company has loaded some attractive new features onto an already well-regarded device.  The new device weighs in at about half the cost per LUT of its predecessor, offers double the density, and eeks out some additional performance in the process.  They’ve also thrown in some user-flash memory capability and beefed up their Live Update field upgrade process.

The non-volatile FPGA arena has become a confusing one in recent years.  A number of dramatically different technologies with completely different characteristics are sailing under the “non-volatile FPGA” flag, forcing designers to dig one level deeper to find out what properties actually accompany the “non-volatile” label.  The oldest and best-known of these are anti-fuse-type devices that rely on one-time programmable metal-to-metal connections for programming.  Anti-fuse devices have long been marketed by Actel and QuickLogic for applications that require some combination of high speed, low static power, radiation immunity, instant power-up, and high security.  Because they are one-time programmable and inherently size-limited, antifuse devices target completely different applications from other non-volatile families.

Following the anti-fuse devices were FPGAs based on flash technology, where flash cells are used in the actual configuration logic.  Actel has marketed these for years under their “ProASIC” brand.  Flash-based FPGAs offer the advantage of reprogrammability over anti-fuse devices, but they suffer from a relative lack of performance.  They share many of anti-fuse’s other desirable characteristics, however.  On the downside, these devices are very complex from a process point of view and generally trail SRAM by a process node or more.  As such, they will probably always trail SRAM-based devices in overall density and performance.

More recently, hybrid devices have been introduced that combine more traditional SRAM-based LUT fabric with on-chip flash memory for configuration.  Lattice’s XP family (and the new XP2 family) both take this approach, along with Altera’s Max II (which still insists it is a CPLD, despite its clearly FPGA-style architecture).  By using on-chip flash configuration instead of external configuration memory, configuration can be accomplished almost instantaneously rather than on the multi-millisecond-scale imposed by JTAG limitations.  Also, because the configuration bitstream is never externalized, design security is higher than with traditional externally-configured SRAM devices.  The primary advantage of this approach compared with full-flash FPGAs is the higher-performance SRAM-based LUT fabric.

Most recently, the non-volatile picture has been confused even more by Xilinx with their introduction of a die-stack device that uses SIP technology to simply stack a Spartan-3 FPGA and a flash configuration die in the same package.  This approach shares many properties with the hybrid flash-with-SRAM design, but gives up configuration speed, as the configuration is still done through the same serial port used for normal SRAM FPGAs.  While design security is improved over SRAM with external flash, the security level is debatable because the flash-to-SRAM connection is still externalized, albeit inside a sealed package.

In creating the new flash/SRAM hybrid Lattice XP2, Lattice had to implement flash memory on the same 90nm die as SRAM FPGA fabric – no small feat.  The payoff is substantial, however, as the density and performance are on-par with other 90nm SRAM FPGA families, and the benefits of non-volatility put XP2 in a league by itself. 

One of the intriguing features of the new XP2 is what Lattice calls “Live Update,” which is a pre-engineered system for field updating your FPGA configuration.  The idea is to give a secure way to reliably transmit and install a bitstream in an FPGA operating field with minimal disruption.  The XP2 has a “dual boot” capability, which essentially lets it fall back into a default configuration if the load of a bad replacement is detected.

The process works like this:  First, an encrypted bitstream is transmitted and loaded into the flash configuration memory while the FPGA is still running from the active configuration in the SRAM fabric.  Next, the I/Os are locked in the appropriate state to keep the system happy during reconfiguration.  Then, using the (very fast) internal configuration capability, the new configuration from flash is loaded into SRAM.  Finally, control of the I/Os is returned to the FPGA.  A “golden” configuration can be stored in an SPI configuration memory, and in the event of an invalid load, the XP2 will automatically load and use the “golden” configuration as a fallback.

For DSP applications, XP2 contains a number of full capability DSP blocks that can do multiply-accumulate in hardware.  The company claims that these blocks can operate at 325 MHz, and the largest device sports 32 of the 18X18 multipliers – enough for some pretty significant DSP acceleration.  One of the other ingredients in DSP acceleration, of course, is RAM.  XP comes with 166K to 885K of EBR SRAM (depending on the device), and, of course, the fabric can be used for “Distributed RAM” for local storage.  While these specs don’t exactly make XP2 a DSP warrior, it certainly is more than adequate for the typical DSP component of a larger design or to add acceleration to an embedded application running on Lattice’s Mico32 soft-core processor.

Because security is one of the big motivators for the adoption of a non-volatile device, Lattice did a good job plumbing the new kid with security features.  First, as we mentioned before, the configuration data is stored in on-chip flash, making invasion difficult to impossible.  The device also has optional security bits that prevent memory readback from the chip.  XP2 includes 128-bit AES encryption with the key stored in secure on-chip flash, and a “flash lock” feature that prevents unauthorized reprogramming.  The device also has a “one-time-programmable” (OTP) mode that can lock it out completely so no further programming or erasure can be done.

Also, on the memory front, Lattice XP2 has a good deal of user-flash included and an innovative scheme to increase the life of that flash (flash has a limited number of write cycles that it can endure).  The scheme, called “FlashBAK,” essentially uses embedded block RAM (EBR) as a cache for the user flash.  Reads and writes are done to the EBR – with the advantage of higher speeds (350MHz) and infinite reads and writes.  During configuration, the contents of flash are mirrored to the EBRs, and the flash is re-written from the EBRs on user command.  Persistent user flash is good for a host of fun things like serial numbers, software for soft-core processors, your favorite recipes… anything you want to still have around after the power cycles.  Lattice has also added serial TAG memory that is built from connecting the JTAG chain to a shift register atop the user flash array.  This allows for some persistent data storage and access outside of security for data like ID codes, version and date stamps, calibration settings and so forth.

By the numbers, Lattice XP2 ranges in density from 5K to 40K LUTs and includes the aforementioned 12 to 32 18X18 multipliers, 166K to 885K block RAM, and from 86 to 540 user pins.  Speaking of pins, XP2 is also available in a very small form-factor 8X8mm 132-ball csBGA package, which, when combined with the single-chipness of the non-volatile FPGA, lets you have a lot of programmable logic capability on very little board area.

Lattice XP2 comes supported with the usual full range of development software, IP, and development boards.  Pricing is estimated at $12 each in quantities of 100K or more for 2008 delivery, with samples available now.  Other XP2 devices are planned for 2007.

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