feature article
Subscribe Now

Serial Commodotization

Altera Arria GX

Anybody familiar with Altera FPGAs knows the GX designation.  It’s the suffix that goes on when the family gets upgraded with high-speed serial transceivers.  First we had Stratix, then Stratix GX.  Next, at 90nm we got Stratix II and then Stratix II GX.  Now the company has announced their 65nm lines.  There’s Stratix III, now Cyclone III, and we’re waiting for the GX and… What’s this?  Arria?  90nm again? Confused?  We’ll sort it out for you.

Altera and archrival Xilinx have long played “Tag, You’re It” with innovations such as cost-optimized devices, low-power features, DSP accelerators, and high-speed serial transceivers.  In each case, the company making the first move did so after carefully weighing the marketing consequences.  In the case of differentiating the low-cost and high-performance FPGA families, this is a delicate dance.  Each company wanted to keep the features in their low-cost family as light as possible – both to optimize cost/margin and to preserve differentiation (and thus avoid cannibalization) of their more expensive high-end device families. 

This balance worked great as long as both companies had the same stakes with making money from their low-cost families and protecting their more traditional high-end offerings.  Unfortunately, a spoiler has entered the ring – in the form of Lattice Semiconductor.  Lattice has no giant business to protect in high-end FPGAs.  They have only recently entered the high-end derby in a serious way.  As a result, Lattice is now making moves that upset the equilibrium.  We have seen Lattice’s full-blown DSP blocks in their low-cost lines almost certainly elicit responses from their larger competitors.  Recently, Xilinx launched a non-volatile FPGA family constructed of a Spartan-3 device die-stacked with a flash configuration memory – almost certainly in response to Lattice’s success with their LatticeXP family. 

Recently, Lattice introduced their new Lattice ECP2M family – busting the trend by including high-speed serial I/O (long considered exclusively a high-end FPGA feature) in a cost-optimized FPGA family.  Now, Altera is apparently the first to respond to this challenge with their announcement of the new Arria GX family.  Arria is certainly more than a check-in-the-box “yes, we’ve got low-cost SerDes too” offering, however.  Altera has clearly put some thought into creating a new, market-viable family that goes after specific, emerging, high-value application areas.

First, cost-optimized SerDes-capable FPGAs are not just a +1 feature to gain advantage in existing markets.  With the rapid adoption of certain high-speed serial standards such as PCI Express, Gigabit Ethernet, and Serial RapidIO, demand has suddenly risen for devices that can handle those standards in high-volume (i.e. cost-sensitive) applications.  With only high-end FPGAs having the capability to handle these standards (at least without the addition of separate, stand-alone PHY devices) a cost/capability gap has opened.

Altera’s new Arria GX addresses this with 5 family members ranging from 21,580 to 90,220 equivalent logic elements and with the 50K element devices going for a paltry $50.  In a break with tradition, these are prices “at launch” and for 25K units – not for the usually-quoted theoretical (and mostly useless) bazillion-unit order 18 months from now.

The new devices don’t have the “Swiss army knife” transceivers we’ve come to associate with high-end FPGAs.  Instead, they’ve focused on PCIe (x1 and x4), Gigabit Ethernet, and Serial RapidIO (1x and 4x) at 1.25 and 2.5Gbps.  Remember our primer on pre-emphasis and equalization?  You won’t need it for these devices.  That’s all handled under the hood, before you take delivery.  Altera says that they aimed Arria GX at the standards that have crossed Geoffrey Moore’s “chasm” and gone into high-volume adoption.  By contrast, their current high-end SerDes-equipped devices – Stratix II GX (Stratix III has not announced a GX variant yet) — are able to handle a much broader set of SerDes standards.

The new family is based on 90nm technology – this is not a surprise, as only Xilinx has announced any 65nm FPGA-based transceivers yet, and their offering does not yet cover the full range of protocols and speeds.  What is a surprise is that the cost-optimized Arria GX is not based on Altera’s Cyclone architecture.  Instead, it uses the adaptive logic module (ALM)-based fabric similar to the company’s Stratix II devices.  “OK,” I hear you ask. “Why isn’t this a new type of Stratix-II GX device, then?”  According to Altera, the answer has to do primarily with performance.  The new Arria GX doesn’t have the horsepower in the fabric that we expect from Stratix II, but it needed more oomph to support SerDes than Cyclone II could muster.  Otherwise, it probably would be called “Cyclone II GX.”  Hence we get a brand new nomenclature, “Arria,” that has a heretofore unseen cost-optimized version of Altera’s wider, faster ALM-based logic fabric.

The Stratix-like similarities don’t end with the fabric and transceivers, however.  Altera has also chosen to go with more expensive (and better signal integrity) flip-chip packaging instead of the wire-bond packaging normally associated with low-cost devices.  Their assertion is that the combination of multiple transceivers, DDR memory interfaces, and 100+ additional user I/Os makes signal integrity an unknown risk in a wire-bond package, where flip-chip mitigates that risk significantly.  Combined with the choice of the higher-speed ALM fabric, we’d expect Arria GX to compare favorably to Lattice’s ECP2M family, although the two companies have not yet released enough data to make an accurate comparison feasible.

Compared with Stratix II GX, however, Arria GX will weigh in with about 35% slower fabric, fewer transceiver channels on the largest devices, slower max transceiver speeds (SII GX runs up to 6.375 Gbps), and (in the largest devices) marginally less other resources like RAM, DSP blocks, and user I/O.

Altera says they expect traction for the new devices in applications such as industrial control, OFDM base stations, and medical imaging, where demand is high for popular SerDes protocols, but cost sensitivity makes high-end FPGAs unattractive.  As an already-cost-optimized family, Altera says they have no plans to release HardCopy structured ASIC conversions for Arria GX.

The new family is supported by Quartus II version 7.1, which is available today, and the first shipments are scheduled for June with production shipments expected by September 2007.

Leave a Reply

featured blogs
Jun 22, 2021
Have you ever been in a situation where the run has started and you realize that you needed to add two more workers, or drop a couple of them? In such cases, you wait for the run to complete, make... [[ Click on the title to access the full blog on the Cadence Community site...
Jun 21, 2021
By James Paris Last Saturday was my son's birthday and we had many things to… The post Time is money'¦so why waste it on bad data? appeared first on Design with Calibre....
Jun 17, 2021
Learn how cloud-based SoC design and functional verification systems such as ZeBu Cloud accelerate networking SoC readiness across both hardware & software. The post The Quest for the Most Advanced Networking SoC: Achieving Breakthrough Verification Efficiency with Clou...
Jun 17, 2021
In today’s blog episode, we would like to introduce our newest White Paper: “System and Component qualifications of VPX solutions, Create a novel, low-cost, easy to build, high reliability test platform for VPX modules“. Over the past year, Samtec has worked...

featured video

Kyocera Super Resolution Printer with ARC EV Vision IP

Sponsored by Synopsys

See the amazing image processing features that Kyocera’s TASKalfa 3554ci brings to their customers.

Click here for more information about DesignWare ARC EV Processors for Embedded Vision

featured paper

Choose a high CMTI gate driver that cuts your SiC switch dead-time

Sponsored by Maxim Integrated

As GaN and SiC FETs begin to replace MOSFET and IGBT technologies in power switching applications, this paper discusses the key considerations when selecting an isolated gate driver. Maxim explains the importance of CMTI and propagation delay skew and presents an isolated gate driver IC ideal for use with these new power transistors.

Click to read more

featured chalk talk

PolarFire SoC FPGA Family

Sponsored by Mouser Electronics and Microchip

FPGA SoCs can solve numerous problems for IoT designers. Now, with the growing momentum behind RISC-V, there are FPGA SoCs that feature RISC-V cores as well as low-power, high-security, and high-reliability. In this episode of Chalk Talk, Amelia Dalton chats with KK from Microchip Technology about the new PolarFire SoC family that is ideal for demanding IoT endpoint applications.

Click here for more information about Microchip Technology PolarFire® SoC FPGA Icicle Kit