The flexibility offered by field-programmable gate arrays (FPGAs) has made design iterations an integral part of the FPGA design process. Traditionally, engineers quickly wrote hardware description language (HDL) for their design, ran synthesis and place-and-route on it, programmed the FPGA and tested design functionality directly in hardware. If a performance issue or a functional bug was discovered, appropriate modifications were made to the HDL, followed by re-synthesis and re-place-and-route to obtain a new FPGA bit-stream and re-testing the hardware. This flow was fast enough to easily allow a few iterations in one day.

With the … Read More → "Three “I”s of FPGA Design: Iterations, Incremental and Intelligent Design Tools"

I have this recurring nightmare. I’m supposed to write a chapter for a book. I’ve pretty much got it done, doing some final editing on the last paragraph, and then on review realize that the first paragraph has changed mysteriously. So I fix it, but then another paragraph changes. I never seem to be able to get all the paragraphs right. And then someone else submits his chapter, and for some reason my chapter gets all screwed up. Of course, that’s about the time I also realize that I forgot that I had … Read More → "Incremental Design Moves Towards Mainstream"

For a long time, the messages coming out of Actel were diverse – their two flavors of non-volatile programmable logic devices, some flash-based and others antifuse-based, had distinctive characteristics that differentiated them from mainstream SRAM-based FPGAs.  They tended to have better resistance to radiation and better design security, they were live at power-up, they were a true single-chip solution because they didn’t require configuration circuitry to support them…

Today, that’s all changed.  There is only one marketing word coming out of Actel these days, and it’s Power – less … Read More → "Actel Powers Down – Again"

ChipX has long spanned the gap between FPGA and ASIC.  Their range of products includes everything from structured ASIC through standard cell, and they’re often called into service when FPGAs can’t cut the mustard because of cost, power, or performance, but a full-blown minimum-geometry ASIC project is beyond the means of the project. 

Now, they’re rolling out something they call “Hybrid ASICs” to make their span even more continuous.  Before we get into specifics, let’s have a brief review of terminology.  FPGAs are … Read More → "Spreading the Span"