Today’s fast-paced chip delivery schedules require that logic designers employ design flows that are versatile enough to take advantage of several implementation technologies. Specification changes, pricing or yield issues, and production ramps can change the target implementation technology for a design. Designers might be required to change FPGA devices or vendors, or move their designs from prototyping in an FPGA to production with an ASIC.

Making a decision on whether to use FPGAs or ASICs is based on several requirements including performance, power, unit volumes and time to market. In some cases, FPGAs are used … Read More → "Unified FPGA-ASIC Design Flow Provides Designers Versatility in Meeting Production Goals"

The low-cost FPGA battle is now officially on fire.  Not that long ago, the FPGA race was two-dimensional – whoever could provide the most programmable logic running at the highest Fmax was the winner.  Considerations like cost, power, and feature sets were almost irrelevant.  The people (telecom infrastructure) buying FPGAs were scrambling to deploy as much bandwidth as they could as quickly as possible.  They had big budgets and bigger power supplies.  The FPGA business was relatively simple.

As the technology has matured and broadened, however, specialization has taken over.  It … Read More → "Pins for Pennies"

On the fading footsteps of the fury of the Supercomputing conference, our minds typically whirl on the world of accelerated computation.  We picture powerful systems based on elegant devices that crunch through complex calculations at an almost inconceivable speed.  When we visualize that, of course, we don’t always think about the fact that the “sea level” of compute power is in an ever-increasing tide surge.  As the common desktop computer climbs ever higher in compute performance, many problems and applications that were once the purview of supercomputers have been conquered by the … Read More → "The New DSP"

“…It works the same as assertions in System Verilog,” he said. 

I quickly nodded my head — maybe too quickly.  “Oh, OK, I see,” I replied, almost before he had finished his sentence.

I wanted to give him confidence that the message was received so he would move on in the conversation.  If I looked puzzled, perplexed or confused – if I showed weakness or hesitation, he might linger in the lounge of this idea.  He might hang around here in the vicinity of trouble.  He might catch the scent of … Read More → "The Secret"

The High Performance Computing (HPC) community recognized the inherent limits of serial processing long ago. In the drive to continually improve the performance of HPC codes, programmers have explored a variety of alternatives, including employing new types of processors, coupling multiple processors, and parallel processing. Initially, these strategies were hindered by slow inter-processor communications and limited ability to parallelize algorithms. As a result, early attempts at alternatives to serial computation could employ only tens of processors. Over time, several innovations (including higher-bandwidth inter-processor links, algorithmic improvements that reduced the amount of data sent across those links, coarse-grain parallelism, and … Read More → "Computational Bottlenecks and Hardware Decisions for FPGAs"

Old wisdom says that too many cooks spoil the broth.  New wisdom says that accomplishing anything really big in high-tech requires a great deal of collaboration.  This week, new wisdom trumped old at the SDR forum as an unlikely coalition consisting of Texas Instruments, Xilinx, Green Hills, Objective  Interface, CRC, and even The MathWorks all had roles in producing a new platform for development of software defined radio (SDR) applications.

Software defined radio is developing into a benchmark challenge for the creators of technology.  The idea is simple enough – take the information … Read More → "Team SDR"