The countdown counter/timer circuit was pretty trivial to code up in VHDL.  My dev board had an old FPGA on it, but it didn’t matter.  The original version of my little design probably used less than 10% of the chip anyway.  I’d enhanced it several times, of course.  The original one loaded a big number into the register and then counted down.  When the countdown reached zero, an audio-frequency square wave was generated at an output pin.  A little amplifier circuit took the digital signal and ran it straight … Read More → "Golden Hammer"

Introduction

Since its ratification in 2005, the SystemVerilog IEEE-1800 standard has experienced broad adoption in the verification and assertion space but has lagged for design constructs. Engineers may be wary of revamping current design methodologies, or they assume that SystemVerilog for design is not relevant to their projects, or they fear that field-programmable gate array (FPGA) synthesis tools do not fully support the new standard. All three of these concerns are either exaggerated or based on misconceptions. SystemVerilog is fully supported by leading synthesis tools, and the new design constructs are in fact relevant … Read More → "How To Implement SystemVerilog for FPGA Design"

Once upon a time, PLD pinouts were an easy thing. Oh, yeah, sorry… for you neophytes, that’s “Programmable Logic Device,” a term once ubiquitous, and still relevant, except that FPGAs are the overwhelmingly dominant survivor. So much so that some people think of PLDs as just the small non-volatile glue-mop-up devices, to paint an ugly mixed-metaphorical picture, even though an FPGA is no less programmable a device. Back in the day, when you were writing your Boolean equations in PALASM for your PAL16L8 (OK, I know I’ve lost a … Read More → "Playing Pin Twister"

We’ve talked many times about the potential of FPGAs in providing incredible amounts of the Good kind of power (computing) while consuming comparatively tiny amounts of the Bad kind of power (“juice”).  When you want a lot of numbers manipulated very quickly with the least possible amount of juice, a highly parallelized datapath implemented in the programmable fabric of an FPGA is hard to beat.  That’s why we have groups like the die-hard fringe of supercomputing – the “reconfigurable computing community” struggling for decades to build a tool infrastructure … Read More → "Merging with Agility"