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Accelerating RTL Analysis & Creation with Spreadsheets

History of the Spreadsheet

In 1979, a young Harvard Business School graduate student envisioned a new methodology to effectively organize and process large amounts of data through variations of parameters to yield an exact what-if analysis of numerical models, utilizing something called a personal computer. The young graduate student, Dan Bricklin, created VisiCalc™, the first killer app for the nascent personal computer industry of the early 1980’s. Today millions of users depend on the progeny of VisiCalc, the most popular being Microsoft Excel™. Financial, scientific, and engineering fields have heavily leveraged the spreadsheet paradigm to organize, manage, analyze, model, and generate numerical and text data. Spreadsheets are now making their way into hardware design.

Mainstream Design Entry/Creation of RTL Designs

In two decades, ASIC/FPGA designs have increased in gate count by many orders of magnitude, and the methods of design entry/creation have moved from text to schematics/graphics and then moved back to text with the advent of hardware description languages (VHDL, Verilog, SystemVerilog, etc) nearly a decade ago. Each step in the evolution of the process of design entry/creation has been for reasons of managing ever larger designs and representing them in the most compact form possible for editing, comprehension, and synthesis into its end product: a logical netlist of gates.

Today’s SOC designs can easily range into the hundreds of millions of gates, being composed of subsystems of multiple processors, memory, and peripherals such as communications cores, multi-gigabit I/O cores, plus the ever present glue logic. Typically an RTL description in VHDL or Verilog is used to define these subsystems, and a team of designers would reuse or modify existing code as well as write new code to define new functionality to suit the next-generation design. The quantity of VHDL or Verilog code to define such designs can range from a few hundred to over a million lines. The primary strategies for managing designs of this size are through the wise use of hierarchy and partitioning. Levels of hierarchy and partitioning of designs lead to many VHDL/Verilog entities/modules and hence many files in which there are inherent dependencies as well as challenges. Utilizing text editors to view, edit, and create a large number of files can certainly be subject to human error; e.g. propagating changes of signal names, misconnections, etc. Methods to allow the designers the ability to work as a team to reuse, create, edit, and ultimately analyze a design can greatly enhance productivity on the front end of the design process.

Extending the Spreadsheet Paradigm to RTL Design

Most people think of spreadsheets as two-dimensional X-Y grids containing cells for the entry of numerical and text data. User-written functions are then used to analyze and manipulate the data. Entering or mapping an RTL design to a spreadsheet format can also be easily accomplished. The interfaces of VHDL or Verilog components (modules/entities) can be defined as rows of signals in the spreadsheet, while modules/entities can be defined by the columns. The resulting two-dimensional matrix of rows and columns form the Interconnect Matrix, both displaying and defining the connectivity between components. Applying the concept of hierarchy to this RTL data matrix, each column representing a component could contain the next lower level of the hierarchy with its own scope of signals and associated components. This spreadsheet approach provides a concise and compact representation of even the most complex of designs.

Advantages of Spreadsheets for RTL Design

As noted above, spreadsheet data is typically analyzed and manipulated by user-written functions. The Interface Based Design (IBD) editor provided by Mentor Graphics HDL Designer Series™ is a new approach for design entry and management, addressing the frustrations and challenges of designers who utilize text-only editors. The IBD editor, used in conjunction with a text editor, reduces complexity and improves the ability to visualize and document new designs, facilitating rapid design entry and fast modification by reducing the time required to describe and connect ports.

IBD augments text-based interconnect descriptions with a compact and flexible spreadsheet format. This spreadsheet style of editing/analysis allows designers to capture a given level of design hierarchy piece by piece. A structure consisting of many components can be captured as a set of signals between small numbers of these components.

IBD is especially suited to teams working on large, complex designs with high pin/signal counts and many interconnections. Since the spreadsheet representation is so compact, a complex netlist can be described rapidly in a minimum of space. This compactness results in the micro- and macro-level details being available during the design process without having to introduce unnecessary levels of hierarchy or create wordy design documentation. This spreadsheet design approach produces accurately generated HDL code without any of the potential errors that could arise from hand-coding such complex interconnects (Figure 1).

Analysis and Understanding for Design and Reuse

HDL Designer Series allows any mix of Verilog and/or VHDL design to be read into the IBD editor. Thus, reading in complex designs for the purposes of analysis or reuse is a simple matter of utilizing the powerful functions of the IBD editor. A flexible filtering mechanism, both predefined and user-generated, is available on any signal or module/entity.

Utilizing this filtering capability, a complex design can be reduced to the relevant components or portion of the design, helping the designer understand its architecture via component-to-component connectivity. Regardless of the size or complexity of the design, tasks such as identifying the number and location of unconnected ports across the entire design are easily accomplished with the editor.

Within the IBD editor, signals and components can be grouped in any fashion to organize the design and to aid in documentation. Grouping can be done hierarchically for both signals and modules/entities, simplifying the view and further providing a method to manage and organize the design data for easy analysis and understanding. Any view of the design, filtered or unfiltered, can be visualized at any level in the form of a block diagram to further aid in understanding and can be effectively used for documentation (Figure 2).

The spreadsheet format, with its ability to instantly analyze and display design connectivity, is not available to those using a text editor alone. The IBD editor greatly accelerates the process of understanding the state of a design.

Creating and Managing Complex Designs

Creating a complex design today involves the reuse of over 80% of an existing or previous generation’s design. As discussed earlier, the IBD editor is a powerful tool in analyzing and understanding a design. Once existing code is well understood, the next step is to create new functionality and merge in the pre-existing code. This task is handled today by a team member responsible for stitching the design together, often at just the top level, creating the structural HDL code. Given that this process is often done either by hand or by in-house scripts and macros, which also need to be maintained and updated, this task can be very error prone.

The IBD editor can be used to create and manage any level of a design. Verilog and/or VHDL components can be simply dragged and dropped into the IBD editor to display all signals/ports for analysis. The editor’s filtering mechanism can be used to show the unconnected ports of any component as a column beneath the component itself. This capability removes any chance of an error in connection due to mistyping or miscommunication of signal specifications.

The team-design features of HDL Designer Series allow a design group to work concurrently via version management tools and techniques, always insuring that the correct versions of components are used. By utilizing the IBD editor to manage the top level of the design, the lower levels can be assigned to the appropriate team members for creation and editing with any editor they choose. In this fashion, the top level of the design is constantly available for each member of the group, enabling the team to refer to top-level connectivity while focusing on their portion of the design. At any time during the design process, a top-level structural HDL file can be automatically created based on the data within the IBD editor. The resulting HDL file is correct by construction and free of any connectivity errors, saving both time and effort in debugging (Figure 3).

Conclusion

There is no avoiding the fact that today’s designs are growing larger and subsequently more complex. Many of today’s designs are system-on-a-chip based and are a combination of soft cores, IP, reused code and custom logic. As the number of signals grows larger and the number of components increases, connecting these at the top level and being able to understand and visualize the design becomes more and more challenging. The IBD editor from HDL Designer Series provides a unique application of the spreadsheet paradigm to RTL design, easing the analysis, understanding, creation and management, as well as providing documentation — greatly improving the productivity of the designer and the design team.

10 thoughts on “Accelerating RTL Analysis & Creation with Spreadsheets”

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  5. Kevin, I am not sure how you became the author of this piece as I am the author of this when I was at Mentor Graphics. Can you please update and provide credit to the proper author, me? Thx, Mike Lee

  6. It is sad that the Electronics DESIGN AUTOMATION industry is so obsessed with synthesis that the need for interconnections at the module level and functional simulation are ignored. Also
    that there is no way to compile an HDL without synthesis, P&R, STA.

    Visual Studio and the Roslyn/C# Compiler have exposed the AST and a Syntax Walker that exposes all references for all objects((modules) and the order of evaluation of every expression(assignment or logical expression).

    If/else , not and conditional assignments can be used as in the HDLs, or Boolean expressions can be used for control logic. Boolean types and expressions are supported.

    The process becomes:
    > define the modules as types
    > reference module variable names or get expression names for inputs
    > use public/private/protected keywords to control accesses to variables
    > get can access variables or expressions(arithmetic, logical)

    Functional simulation/modelling consists of compiling and running the program since
    the variables and expressions have been compiled and ready for execution.

    Debug is essentially the same as for any program because the same expressions and variables are used.

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