Want your DSP design to consume less power? Join Amelia Dalton as she talks with Tim Vanevenhoven of Xilinx about new methods for estimating and reducing power consumption in FPGA-based DSP … Read More → "Power Estimation in High-Level DSP Design Flow"
It’s crunch time. The prototype for our board has been spun and is in transit back to our lab for testing. The project is already two weeks behind schedule thanks to late changes to the spec and problems discovered during signal integrity analysis of the layout. It’s been good for me because, quite frankly, I needed those two weeks to get my test bench to where I am satisfied that I have done due diligence to the simulation.
Read More → "The Simulizater Is Not God"
We’ve talked about power a lot on these pages over the past year. We’ve told about advances in power optimization and estimation, struggles with leakage current at smaller geometries, clock gating, configuration peaks, and a bunch of other hot topics in cool FPGA design. All of these late-breaking developments are wonderful if you already know the starting point. However, many of our readers have pointed out that we could use a little more background. It’s not that exciting to find out that leakage current has been reduced by 50% if you don’t know what the leakage … Read More → "Power Primer"
Picture this architecture – a high speed application processor doing control coupled to an accelerator comprised of a mass of processing elements ready to power-parallelize compute-intensive components of a complex problem. Sound familiar? Supercomputers have taken advantage of acceleration using schemes like this for a while. People using FPGAs for co-processors do it all the time.
Now, picture a new chip with 1.4 billion transistors, an array of 240 cores, and a processing throughput equivalent to about 1 TeraFLOPS. Many readers of this publication would probably guess … Read More → "A Passel of Processors"
You never know with CEOs these days. There was a time when there was a certain order to things, a level of formality. CEOs would set themselves apart, and, in emulation of that, so would their teams. Mahogany Row represented the corporate pantheon, and veneration was the expected order of the day. Fallibility would be, if not brushed off outright as beyond possibility, at least not broached. We’ve probably all known some old-school CEOs. The ones you can’t speak to unless spoken to first. The ones that like to keep their execs guessing what it … Read More → "Executive Profile"
This article has been in production for some time. It was going to be so simple: chat to two of the leading pundits on system safety and pull together a quick piece of “compare and contrast.” Just to add to the timeliness, there has been a very genteel firefight over the role of the IEC 61508 standard on the leading system safety newsgroup (http://www.cs.york.ac.uk/hise/sc_list.php), and, sadly, Air France flight 447 has disappeared, leading … Read More → "Engineering or Craft"
Introduction
Moore’s law continues to drive both chip complexity and performance to new highs every year, and continues to stress and periodically “break” existing design flows. Fortunately for EDA users, the same shrinking geometries that make their design problems tougher are also helping to improve the performance for their EDA tools.
But when it comes to functional verification, traditionally the largest bottleneck in the design process, software-based approaches … Read More → "ZeBu™: A Unified Verification Approach for Hardware Designers and Embedded Software Developers"
When most of us went to engineering school, we planned to immerse ourselves in the ocean of technology. Our education started with foundations of mathematics and science, and then, like some giant tech-history-TiVo, fast-forwarded us through centuries of experience and innovation to get us to a point somewhere near the state-of-the-art at the time of our graduation.
We soon learned that our engineering degree was simply a license to learn, however. In an environment of exponential change (as evidenced by Moore’s Law), the actual technology we mastered in our educational process was probably obsolete … Read More → "Climbing the Pyramid"
The concept of clocking a register is pretty simple. It’s Logic Design 101 stuff. Having an entire system controlled by a uniform clock makes accessible that which would otherwise be an intractable problem. It’s like adding traffic lights downtown to keep traffic from getting completely chaotic.
A whole discipline has grown out of this very basic concept: that of synchronous design. An entire ecosystem of tools and techniques has been built around some very fundamental assumptions of how to design such circuits. And as the circuits have gotten bigger, clock tree synthesis (CTS) has … Read More → "Skew This!"
Some things were just made to go together (peanut butter and jelly) and some just weren’t, (those two teenagers in the Classmates.com pop-up ads). Now the embedded industry has a new mashup: Intel and Wind River Systems. The #1 chipmaker has hooked up with the #1 embedded-software company. Is this a match made in heaven or a disaster waiting to happen?
So far, I like the deal. It draws public attention to the oft-neglected embedded market, it gives Linux a boost (possibly at the expense of Microsoft), and it underscores Intel’s commitment to embedded … Read More → "What the Hell Were They Thinking?!"
