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Cool and Groovy at DAC

I  have now attended more than half of the 41 annual Design Automation Conferences. One of the things I’ve noticed during those twenty-odd years is that DAC started at the end of the design flow and moved forward. From the days when the hot topics in design automation were replacing tape and glass with Calma systems, the focus of DAC has been subjects closest to silicon. This, in turn, set the tone for the attendees as DAC’s content pushed its way from implementation details at the transistor level toward higher levels of design abstraction.

< … Read More → "Cool and Groovy at DAC"

DAC’s Dangerous Undertones

The 41st Design Automation Conference in San Diego last week wasn’t a bad conference. In fact, it was quite a good one. According to the program, there were a record number of papers submitted to the technical conference, and the selection panel had to be “more selective than ever” in choosing the elite few that were granted a session at DAC.

As a trade show, however, DAC is telegraphing ominous signals to the industry that supports it. Declining ASIC design starts, increasingly complex technical challenges, and rapidly improving alternative solutions threaten the very … Read More → "DAC’s Dangerous Undertones"

Racing for the Gap

As suppliers jockey for position in offering products that hit the gap between the flexibility and risk-free design offered by FPGA and the performance and unit-cost advantages of cell-based ASIC, unlikely alliances are inevitable. In this case, ASIC design tool leader Synopsys is teaming with leading FPGA vendor Altera to jointly develop solutions for the design and production of Structured ASICs.

Altera has long touted their HardCopy structured ASIC as a clean cost-reduction path from an FPGA-based development, prototype, and early production platform to a cost-reduced, performance-optimized mask-programmed equivalent. Altera is betting that the advantages of programmable … Read More → "Racing for the Gap"

Virtex-4

In the 90s, it was obvious that within the decade, exploding gate counts would outstrip our ability to design. The popular debate topic at that time was how the “white space” would be used. “White space” represented the difference between the number of available gates on a semiconductor device, and the number of gates we could successfully design correctly using current methodologies. Speculation ran rampant that large amounts of RAM, immense IP blocks, and system-on-chip integration would help us fill some of the space, but the overall question remained.

When FPGAs burst onto … Read More → "Virtex-4"

Leveraging On-Chip Debug for VME

Introduction

Galileo Avionica needed an easy-to-use VME BUS monitor that could be used by both hardware and software engineers working on VME-based projects. Using a plug-in VME board with an Altera FPGA, embedded DiaLite virtual instrumentation from Temento Systems, and a TCL/TK-based custom human interface, an innovative solution was crafted that allows simple, multi-use analysis of the VME bus by engineers from different disciplines with widely varied levels of experience and expertise.

This article describes how DiaLite Instrumentation (DLI) was used to build a custom tool by taking advantage of the capability … Read More → "Leveraging On-Chip Debug for VME"

Catapult C

Electronic design automation has its own secret little cold fusion. An innovation that everyone quietly hopes is possible but publicly disavows. A development that would make life beautiful, dogs and cats live happily together, and money grow on trees. This missing link is “behavioral synthesis,” the direct compilation of untimed algorithmic descriptions into practical hardware architectures. Once this is possible, digital hardware designers, the micro-architectural mavens that create much of the magic in today’s ASIC and FPGA designs, will no longer be necessary. All of their relevant expertise, tricks and techniques will be … Read More → "Catapult C"

FPGA Simulation

When someone uses the words “verification” and “FPGA” in the same sentence, I’m always suspicious. In the ASIC design world, where risk avoidance is everything, “verification” is a sacred term. “Verification” is the long pole in the tent, the most time-consuming phase of the design cycle. “Verification” is what you do to protect your job so you’re not blamed with an expensive and time-consuming re-spin of an ASIC design. “Verification” is what EDA companies have learned to trust as their bread-and-butter. … Read More → "FPGA Simulation"

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